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| LatticeECP2/M Family Data Sheet DS1006 Version 03.3, August 2008 LatticeECP2/M Family Data Sheet Introduction June 2008 Data Sheet DS1006 Features High Logic Density for System Integration * 6K to 95K LUTs * 90 to 583 I/Os Pre-Engineered Source Synchronous I/O * DDR registers in I/O cells * Dedicated gearing logic * Source synchronous standards support - SPI4.2, SFI4 (DDR Mode), XGMII - High Speed ADC/DAC devices * Dedicated DDR and DDR2 memory support - DDR1: 400 (200MHz) / DDR2: 533 (266MHz) * Dedicated DQS support Embedded SERDES (LatticeECP2M Only) * Data Rates 250 Mbps to 3.125 Gbps * Up to 16 channels per device PCI Express, Ethernet (1GbE, SGMII), OBSAI, CPRI and Serial RapidIO. sysDSPTM Block * 3 to 42 blocks for high performance multiply and accumulate * Each block supports - One 36x36, four 18X18 or eight 9X9 multipliers Programmable sysI/OTM Buffer Supports Wide Range Of Interfaces * * * * * * * * * * * LVTTL and LVCMOS 33/25/18/15/12 SSTL 3/2/18 I, II HSTL15 I and HSTL18 I, II PCI and Differential HSTL, SSTL LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL 1149.1 Boundary Scan compliant Dedicated bank for configuration I/Os SPI boot flash interface Dual boot images supported TransFRTM I/O for simple field updates Soft Error Detect macro embedded Flexible Memory Resources * 55Kbits to 5308Kbits sysMEMTM Embedded Block RAM (EBR) - 18Kbit block - Single, pseudo dual and true dual port - Byte Enable Mode support * 12K to 202Kbits distributed RAM - Single port and pseudo dual port Flexible Device Configuration sysCLOCK Analog PLLs and DLLs * Two GPLLs and up to six SPLLs per device - Clock multiply, divide, phase & delay adjust - Dynamic PLL adjustment * Two general purpose DLLs per device Optional Bitstream Encryption (LatticeECP2/M "S" Versions Only) System Level Support * ispTRACYTM internal logic analyzer capability * On-chip oscillator for initialization & general use * 1.2V power supply Table 1-1. LatticeECP2 (Including "S-Series") Family Selection Guide Device LUTs (K) Distributed RAM (Kbits) EBR SRAM (Kbits) EBR SRAM Blocks sysDSP Blocks 18x18 Multipliers GPLL + SPLL + DLL Maximum Available I/O Packages and I/O Combinations 144-pin TQFP (20 x 20 mm) 208-pin PQFP (28 x 28 mm) 256-ball fpBGA (17 x 17 mm) 484-ball fpBGA (23 x 23 mm) 672-ball fpBGA (27 x 27 mm) 900-ball fpBGA (31 x 31 mm) 190 90 93 131 193 297 131 193 331 402 331 450 339 500 500 583 ECP2-6 6 12 55 3 3 12 2+0+2 190 ECP2-12 12 24 221 12 6 24 2+0+2 297 ECP2-20 21 42 276 15 7 28 2+0+2 402 ECP2-35 32 64 332 18 8 32 2+0+2 450 ECP2-50 48 96 387 21 18 72 2+2+2 500 ECP2-70 68 136 1032 60 22 88 2+4+2 583 (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1006 Introduction_01.7 Lattice Semiconductor Introduction LatticeECP2/M Family Data Sheet Table 1-2. LatticeECP2M (Including "S-Series") Family Selection Guide Device LUTs (K) sysMEM Blocks (18kb) Embedded Memory (Kbits) Distributed Memory (Kbits) sysDSP Blocks 18x18 Multipliers GPLL+SPLL+DLL Maximum Available I/O 256-ball fpBGA (17 x 17 mm) 484-ball fpBGA (23 x 23 mm) 672-ball fpBGA (27 x 27 mm) 900-ball fpBGA (31 x 31 mm) 1152-ball fpBGA (35 x 35 mm) ECP2M20 19 66 1217 41 6 24 2+6+2 304 4 / 140 4 / 304 ECP2M35 34 114 2101 71 8 32 2+6+2 410 4 / 140 4 / 303 4 / 410 4 / 270 8 / 372 8 / 410 16 / 416 16 / 436 16 / 416 16 / 520 ECP2M50 48 225 4147 101 22 88 2+6+2 410 ECP2M70 67 246 4534 145 24 96 2+6+2 436 ECP2M100 95 288 5308 202 42 168 2+6+2 520 Packages and SERDES / I/O Combinations Introduction The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm technology. The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configuration support, including encryption ("S" versions only) and dual boot capabilities. The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low transmission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization settings make SERDES suitable for chip to chip and small form factor backplane applications. The ispLEVER(R) design tool suite from Lattice allows large complex designs to be efficiently implemented using the LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORETM modules for the LatticeECP2/M family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 LatticeECP2/M Family Data Sheet Architecture August 2008 Data Sheet DS1006 Architecture Overview Each LatticeECP2/M device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEMTM Embedded Block RAM (EBR) and rows of sysDSPTM Digital Signal Processing blocks, as shown in Figure 2-1. In addition, the LatticeECP2M family contains SERDES Quads in one or more of the corners. Figure 2-2 shows the block diagram of ECP2M20 with one quad. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a twodimensional array. Only one type of block is used per row. The LatticeECP2/M devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18K fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addition, LatticeECP2/M devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. The LatticeECP2M devices feature up to 16 embedded 3.125Gbps SERDES (Serializer / Deserializer) channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of four SERDES channels along with its Physical Coding Sub-layer (PCS) block, creates a quad. The functionality of the SERDES/PCS Quads can be controlled by memory cells set during device configuration or by registers that are addressable during device operation. The registers in every quad can be programmed by a soft IP interface, referred to as the SERDES Client Interface (SCI). These quads (up to four) are located at the corners of the devices. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the LatticeECP2/M devices are arranged in eight banks, allowing the implementation of a wide variety of I/O standards. In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as SPI4.2, along with memory interfaces including DDR2. Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP2/M architecture provides two General PLLs (GPLL) and up to six Standard PLLs (SPLL) per device. In addition, each LatticeECP2/M family member provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottommost EBR row; the DLL block is located towards the edge of the device. The SPLL blocks are located at the end of the other EBR/DSP rows. The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual boot support is located toward the center of this EBR row. The Ball Grid Array (BGA) package devices in the LatticeECP2/M family supports a sysCONFIGTM port located in the corner between banks four and five, which allows for serial or parallel device configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The LatticeECP2/M devices use 1.2V as their core voltage. (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1006 Architecture_01.9 Lattice Semiconductor Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level) Programmable Function Units (PFUs) Architecture LatticeECP2/M Family Data Sheet Flexible sysIO Buffers: LVCMOS, HSTL, SSTL, LVDS, and other standards sysDSP Blocks Multiply and Accumulate Support Pre-engineered source synchronous support * DDR1/2 * SPI4.2 * ADC/DAC devices sysMEM Block RAM 18kbit Dual Port Flexible routing optimized for speed, cost and routability sysCLOCK PLLs and DLLs Frequency Synthesis and Clock Alignment Configuration logic, including dual boot and encryption. On-chip oscillator and soft-error detection. Configuration port Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level) SERDES Flexible sysIO Buffers: LVCMOS, HSTL SSTL, LVDS Programmable Function Units (PFUs) Pre-Engineered Source Synchronous Support * DDR1/2 * SPI4.2 * ADC/DAC devices Channel 3 Channel 2 Channel 1 Channel 0 DSP Blocks Multiply & Accumulate Support sysCLOCK SPLLs Configuration Logic, Including dual boot and encryption, and soft-error detection sysMEM Block RAM 18kbit Dual Port Flexible Routing optimized for speed, cost & routability sysCLOCK GPLLs & GDLLs Frequency Synthesis & Clock Alignment Configuration Port On-Chip Oscillator 2-2 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet PFU Blocks The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. Figure 2-3. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 LUT4 Slice 0 Slice 1 Slice 2 Slice 3 D D D D D D FF FF FF FF FF FF To Routing Slice Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in the PFF. Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. Table 2-1. Resources and Modes Available per Slice PFU BLock Slice Slice 0 Slice 1 Slice 2 Slice 3 Resources 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers 2 LUT4s Modes Logic, Ripple, RAM, ROM Logic, Ripple, ROM Logic, Ripple, RAM, ROM Logic, ROM Resources 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers 2 LUT4s and 2 Registers 2 LUT4s PFF Block Modes Logic, Ripple, ROM Logic, Ripple, ROM Logic, Ripple, ROM Logic, ROM Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2. 2-3 Lattice Semiconductor Figure 2-4. Slice Diagram FCO To Different Slice/PFU Architecture LatticeECP2/M Family Data Sheet SLICE FXB FXA A1 B1 C1 D1 CO LUT4 & CARRY* CI OFX1 F/SUM D FF* To Routing LUT5 Mux F1 Q1 M1 M0 From Routing OFX0 A0 B0 C0 D0 CO LUT4 & CARRY* CI F0 F/SUM D FF* Q0 CE CLK LSR * Not in Slice 3 FCI From Different Slice/PFU For Slices 0 and 2, memory control signals are generated from Slice 1 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data WAD [A:D] is a 4bit address from slice 1 LUT input Table 2-2. Slice Signal Descriptions Function Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Multi-purpose Control signal Control signal Control signal Inter-PFU signal Inter-slice signal Inter-slice signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names A0, B0, C0, D0 A1, B1, C1, D1 M0 M1 CE LSR CLK FC FXA FXB F0, F1 Q0, Q1 OFX0 OFX1 FCO Inputs to LUT4 Inputs to LUT4 Multipurpose Input Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry-in1 Intermediate signal to generate LUT6 and LUT7 Intermediate signal to generate LUT6 and LUT7 LUT4 output register bypass signals Register outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the slice Slice 2 of each PFU is the fast carry chain output1 Description 1. See Figure 2-4 for connection details. 2. Requires two PFUs. 2-4 Lattice Semiconductor Modes of Operation Architecture LatticeECP2/M Family Data Sheet Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four slices. Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each slice: * Addition 2-bit * Subtraction 2-bit * Add/Subtract 2-bit using dynamic control * Up counter 2-bit * Down counter 2-bit * Up/Down counter with Async clear * Up/Down counter with preload (sync) * Ripple mode multiplier building block * Multiplier support * Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. RAM Mode In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit pseudo dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in LatticeECP2/M devices, please see the list of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required to Implement Distributed RAM SPR 16X4 Number of slices 3 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM PDPR 16X4 3 2-5 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. Routing There are many resources provided in the LatticeECP2/M devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and x6 resources are buffered, allowing the routing of both short and long connections between PFUs. The LatticeECP2/M family has an enhanced routing architecture that produces a compact design. The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysCLOCK Phase Locked Loops (GPLL/SPLL) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All the devices in the LatticeECP2/M family support two General Purpose PLLs (GPLLs) which are full-featured PLLs. In addition, some of the larger devices have two to six Standard PLLs (SPLLs) that have a subset of GPLL functionality. General Purpose PLL (GPLL) The architecture of the GPLL is shown in Figure 2-5. A description of the GPLL functionality follows. CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP or from a user clock PIN/ logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference frequency. The Delay Adjust Block adjusts either the delays of the reference or feedback signals. The Delay Adjust Block can either be programmed during configuration or can be adjusted dynamically. The setup, hold or clock-to-out times of the device can be improved by programming a delay in the feedback or input path of the PLL, which will advance or delay the output clock with reference to the input clock. Following the Delay Adjust Block, both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. In this block the difference between the input path and feedback signals is used to control the frequency and phase of the oscillator. A LOCK signal is generated by the VCO to indicate that the VCO has locked onto the input clock signal. In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and not relock until the tLOCK parameter has been satisfied. LatticeECP2/M devices have two dedicated pins on the left and right edges of the device for connecting optional external capacitors to the VCO. This allows the PLLs to operate at a lower frequency. This is a shared resource that can only be used by one PLL (GPLL or SPLL) per side. The output of the VCO then enters the post-scalar divider. The post-scalar divider allows the VCO to operate at higher frequencies than the clock output (CLKOP), thereby increasing the frequency range. A secondary divider takes the CLKOP signal and uses it to derive lower frequency outputs (CLKOK). The Phase/Duty Select block adjusts the phase and duty cycle of the CLKOP signal and generates the CLKOS signal. The phase/duty cycle setting can be pre-programmed or dynamically adjusted. The primary output from the post scalar divider CLKOP along with the outputs from the secondary divider (CLKOK) and Phase/Duty select (CLKOS) are fed to the clock distribution network. 2-6 Lattice Semiconductor Figure 2-5. General Purpose PLL (GPLL) Diagram Architecture LatticeECP2/M Family Data Sheet Dynamic Delay Adjustment Dynamic Adjustment LOCK CLKI (from routing or external pin) CLKFB from CLKOP (PLL internal), from clock net(CLKOP) or from a user clock (pin or logic) RST RSTK Input Clock Divider (CLKI) Delay Adjust Feedback Divider (CLKFB) CLKOS Voltage Controlled Oscillator Post Scalar Divider (CLKOP) Phase/Duty Select CLKOP CLKOK Secondary Divider (CLKOK) PLLCAP External Pin (Optional External Capacitor) Standard PLL (SPLL) Some of the larger devices have two to six Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but without delay adjustment capability. SPLLs also provide different parametric specifications. For more information, please see the list of additional technical documentation at the end of this data sheet. Table 2-4 provides a description of the signals in the GPLL and SPLL blocks. Table 2-4. GPLL and SPLL Blocks Signal Descriptions Signal CLKI CLKFB RST RSTK CLKOS CLKOP CLKOK LOCK DDAMODE1 DDAIZR1 DDAILAG1 DDAIDEL[2:0]1 DPA MODES DPHASE [3:0] DDDUTY [3:0] I/O I I I I O O O O I I I I I I -- Clock input from external pin or routing PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) "1" to reset PLL counters, VCO, charge pumps and M-dividers "1" to reset K-divider PLL output clock to clock tree (phase shifted/duty cycle changed) PLL output clock to clock tree (no phase shift) PLL output to clock tree through secondary clock divider "1" indicates PLL LOCK to CLKI Dynamic Delay Enable. "1": Pin control (dynamic), "0": Fuse Control (static) Dynamic Delay Zero. "1": delay = 0, "0": delay = on Dynamic Delay Lag/Lead. "1": Lead, "0": Lag Dynamic Delay Input DPA (Dynamic Phase Adjust/Duty Cycle Select) mode DPA Phase Adjust inputs DPA Duty Cycle Select inputs Description 1. These signals are not available in SPLL. 2-7 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet Delay Locked Loops (DLL) In addition to PLLs, the LatticeECP2/M family of devices has two DLLs per device. CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference input of the Phase Frequency Detector (PFD) input mux. The reference signal for the PFD can also be generated from the Delay Chain and CLKFB signals. The feedback input to the PFD is generated from the CLKFB pin, CLKI or from tapped signal from the Delay chain. The PFD produces a binary number proportional to the phase and frequency difference between the reference and feedback signals. This binary output of the PFD is fed into a Arithmetic Logic Unit (ALU). Based on these inputs, the ALU determines the correct digital control codes to send to the delay chain in order to better match the reference and feedback signals. This digital code from the ALU is also transmitted via the Digital Control bus (DCNTL) bus to its associated DLLDELA delay block. The ALUHOLD input allows the user to suspend the ALU output at its current value. The UDDCNTL signal allows the user to latch the current value on the DCNTL bus. The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. Both the CLKOS and CLKOP outputs are available with optional duty cycle correction. Divide by two and divide by four frequencies are available at CLKOS. The LOCK output signal is asserted when the DLL is locked. Figure 2-6 shows the DLL block diagram and Table 2-5 provides a description of the DLL inputs and outputs. The user can configure the DLL for many common functions such as time reference delay mode and clock injection removal mode. Lattice provides primitives in its design tools for these functions. For more information about the DLL, please see the list of additional technical documentation at the end of this data sheet. Figure 2-6. Delay Locked Loop Diagram (DLL) ALUHOLD Delay Chain Delay0 Delay1 Duty Cycle 50% CLKOP /4 /2 (from routing or external pin) Delay2 Reference Phase Frequency Detector Feedback Lock Detect Arithmetic Logic Unit Output Muxes Duty Cycle 50% Delay3 Delay4 CLKI from CLKOP (DLL internal), from clock net (CLKOP) or from a user clock (pin or logic) CLKOS /4 /2 CLKFB UDDCNTL RSTN LOCK Digital Control Output 9 DCNTL 2-8 Lattice Semiconductor Table 2-5. DLL Signals Signal CLKI CLKFB RSTN ALUHOLD UDDCNTL DCNTL[8:0] CLKOP CLKOS LOCK I/O I I I I I O O O O Clock input from external pin or routing Architecture LatticeECP2/M Family Data Sheet Description DLL feed input from DLL output, clock net, routing or external pin Active low synchronous reset Active high freezes the ALU Synchronous enable signal (hold high for two cycles) from routing Encoded digital control signals for PIC INDEL and slave delay calibration The primary clock output The secondary clock output with fine phase shift and/or division by 2 or by 4 Active high phase lock indicator DLLDELA Delay Block Closely associated with each DLL is a DLLDELA block. This is a delay block consisting of a delay line with taps and a selection scheme that selects one of the taps. The DCNTL[8:0] bus controls the delay of the CLKO signal. Typically this is the delay setting that the DLL uses to achieve phase alignment. This results in the delay providing a calibrated 90 phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data. The CLKO signal feeds the edge clock network. Figure 2-7 shows the connections between the DLL block and the DLLDELA delay block. For more information, please see the list of additional technical documentation at the end of this data sheet. Figure 2-7. DLLDELA Delay Block PLL_PIO Routing Routing DLL_PIO * CLKI CLKOP CLKOS DLL Block CLKFB_CK CLKOP GDLLFB_PIO ECLK1 DCNTL[8:0] LOCK * CLKFB * * Software selectable CLKI DLLDELA Delay Block CLKO PLL/DLL Cascading LatticeECP2/M devices have been designed to allow certain combinations of PLL (GPLL and SPLL) and DLL cascading. The allowable combinations are: * PLL to PLL supported * PLL to DLL supported 2-9 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet The DLLs in the LatticeECP2/M are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applications to utilize the unique benefits of both DLLs and PLLs. For further information about the DLL, please see the list of additional technical documentation at the end of this data sheet. GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only) All LatticeECP2M devices contain two GDLLs, two GPLLs and six SPLLs, arranged in quadrants as shown in Figure 2-8. In the LatticeECP2M devices GPLLs, SPLLs and GDLLs share their input pins. Figure 2-8 shows the sharing of SPLLs input pin connections in the upper two quadrants and the sharing of GDLL, GPLL and SPLL input pin connections in the lower two quadrants. Figure 2-8. Sharing of PIO Pins by GPLL, SPLL and GDLL in LatticeECP2M Devices SPLL_PIO SPLL SPLL SPLL_PIO SPLL_PIO SPLL Upper Left Quadrant Lower Left Quadrant SPLL Upper Right Quadrant Lower Right Quadrant SPLL_PIO GPLL_PIO GPLL GPLL GPLL_PIO GDLL_PIO GDLL GDLL GDLL_PIO SPLL_PIO SPLL SPLL SPLL_PIO Clock Dividers LatticeECP2/M devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a /2, /4 or /8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, DLLDELA delay blocks, routing or from an external clock input. The clock divider outputs serve as primary clock sources and feed into the clock distribution network. The Reset (RST) control signal resets input and synchronously forces all outputs to low. The RELEASE signal releases outputs synchronously to the input clock. For further information about clock dividers, please see the list of additional technical documentation at the end of this data sheet. Figure 2-9 shows the clock divider connections. 2-10 Lattice Semiconductor Figure 2-9. Clock Divider Connections PLL PAD Routing CLKO CLKOP (GPLL) CLKOP (DLL) CLKOS (GPLL) CLKOS (DLL) Architecture LatticeECP2/M Family Data Sheet /1 /2 CLKDIV /4 RST RELEASE /8 Clock Distribution Network LatticeECP2/M devices have eight quadrant-based primary clocks and eight flexible region-based secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high speed interfaces. These clock inputs are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These clock inputs are fed throughout the chip via a clock distribution system. Primary Clock Sources LatticeECP2/M devices derive clocks from five primary sources: PLL (GPLL and SPLL) outputs, DLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LatticeECP2/M devices have two to eight sysCLOCK PLLs and two DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side of the device, with the exception of the LatticeECP2M 256-fpBGA package devices which have six dedicated clock inputs on the device. Figure 2-10 shows the primary clock sources. 2-11 Lattice Semiconductor Figure 2-10. Primary Clock Sources for ECP2-50 Clock Input Clock Input Architecture LatticeECP2/M Family Data Sheet From Routing PLL Input SPLL SPLL PLL Input CLK DIV CLK DIV Clock Input Clock Input Primary Clock Sources to Eight Quadrant Clock Selection Clock Input Clock Input DLL Input DLL DLL DLL Input PLL Input GPLL GPLL PLL Input From Routing Clock Input Clock Input Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device have six SPLLs. 2-12 Lattice Semiconductor Secondary Clock/Control Sources Architecture LatticeECP2/M Family Data Sheet LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-11 shows the secondary clock sources. Figure 2-11. Secondary Clock Sources Clock Input Clock Input From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing Clock Input Clock Input Secondary Clock Sources Clock Input Clock Input From Routing From Routing From Routing From Routing From Routing From Routing Clock Input Clock Input From Routing From Routing 2-13 Lattice Semiconductor Edge Clock Sources Architecture LatticeECP2/M Family Data Sheet Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be driven from adjacent edge clock PIOs, primary clock PIOs, PLLs/DLLs and clock dividers as shown in Figure 2-12. Figure 2-12. Edge Clock Sources Clock Input From Routing Clock Input From Routing Sources for top edge clocks From Routing Clock Input Clock Input From Routing DLLDELA From Routing Clock Input Clock Input Eight Edge Clocks (ECLK) Two Clocks per Edge From Routing DLLDELA DLL Input PLL Input DLL DLL DLL Input PLL Input GPLL GPLL Sources for left edge clocks Sources for right edge clocks Sources for bottom edge clocks From Routing Clock Input Clock Input From Routing 2-14 Lattice Semiconductor Primary Clock Routing Architecture LatticeECP2/M Family Data Sheet The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally Figure 2-13. Per Quadrant Primary Clock Selection Primary Clock Sources: PLLs + DLLs + CLKDIVs + PIOs + Routing 35:1 35:1 35:1 35:1 35:1 35:1 32:1 32:1 32:1 32:1 DCS CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 DCS CLK7 8 Primary Clocks (CLK0 to CLK7) per Quadrant Dynamic Clock Select (DCS) The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is toggled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 2-13). Figure 2-14 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, please see the list of additional technical documentation at the end of this data sheet. Figure 2-14. DCS Waveforms CLK0 CLK1 SEL DCSOUT Secondary Clock/Control Routing Secondary clocks in the LatticeECP2 devices are region-based resources. The benefit of region-based resources is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR/DSP rows and a special vertical routing channel bound the secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-15 shows 2-15 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet this special vertical routing channel and the eight secondary clock regions for the ECP2-50. LatticeECP2 devices have four secondary clocks (SC0 to SC3) which are distrubed to every region. The secondary clock muxes are located in the center of the device. Figure 2-16 shows the mux structure of the secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for high fan-out signals. Figure 2-15. Secondary Clock Regions ECP2-50 I/O Bank 0 I/O Bank 1 Vertical Routing Channel Regional Boundary Secondary Clock Region 1 I/O Bank 7 Secondary Clock Region 5 DSP Row Regional Boundary I/O Bank 2 Secondary Clock Region 2 Secondary Clock Region 6 I/O Bank 6 Secondary Clock Region 3 Secondary Clock Region 7 I/O Bank 3 DSP Row Regional Boundary Secondary Clock Region 4 Secondary Clock Region 8 EBR Row Regional Boundary Bank 8 I/O Bank 5 I/O Bank 4 2-16 Lattice Semiconductor Figure 2-16. Secondary Clock Selection Architecture LatticeECP2/M Family Data Sheet Secondary Clock Feedlines: 8 PIOs + 16 Routing 24:1 24:1 24:1 24:1 24:1 24:1 24:1 24:1 SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 4 Secondary Clocks/CE/LSR (SC0 to SC3) per Region Clock/Control 4 High Fan-out Data Signals (SC4 to SC7) per Region High Fan-out Data Slice Clock Selection Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used as a clock input to the slices via routing. Slice controls are generated from the secondary clocks or other signals connected via routing. If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3 does not have any registers; therefore it does not have the clock or control muxes. Figure 2-17. Slice0 through Slice2 Clock Selection Primary Clock 8 Secondary Clock 4 Routing 12 Vcc 1 Clock to Slice 25:1 2-17 Lattice Semiconductor Figure 2-18. Slice0 through Slice2 Control Selection Architecture LatticeECP2/M Family Data Sheet Secondary Clock 3 Slice Control Routing 12 Vcc 1 16:1 Edge Clock Routing LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Different PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides of the device. Figure 2-19 shows the selection muxes for these clocks. Figure 2-19. Edge Clock Mux Connections Top and Bottom Edge Clocks ECLK1/ ECLK2 (Both Mux) Routing Clock Input Pad Input Pad GPLL Input Pad DLL Output CLKOP GPLL Output CLKOP Routing CLKO Left and Right Edge Clocks ECLK1 Input Pad GPLL Input Pad DLL Output CLKOS GPLL Output CLKOS Routing CLKO Left and Right Edge Clocks ECLK2 2-18 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet sysMEM Memory LatticeECP2/M devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of an 18Kbit RAM with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. FIFOs can be implemented in sysMEM EBR blocks by implementing support logic with PFUs. The EBR block facilitates parity checking by supporting an optional parity bit for each data byte. EBR blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. Table 2-6. sysMEM Block Configurations Memory Mode Configurations 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 Single Port True Dual Port Pseudo Dual Port Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. EBR memory supports two forms of write behavior for single port or dual port operation: 1. Normal - Data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2-19 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet 2. Write Through - A copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-20. Figure 2-20. Memory Core Reset Memory Core D SET Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable For further information about the sysMEM EBR block, please see the the list of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-21. The GSR input to the EBR is always asynchronous. Figure 2-21. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. 2-20 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becomes active. These instructions apply to all EBR RAM and ROM implementations. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. sysDSPTM Block The LatticeECP2/M family provides a sysDSP block, making it ideally suited for low cost, high performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and decoders. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. sysDSP Block Approach Compared to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. The LatticeECP2/M, on the other hand, has many DSP blocks that support different datawidths. This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-22 compares the fully serial and the mixed parallel and serial implementations. Figure 2-22. Comparison of General DSP and LatticeECP2/M Approaches Operand A Operand A Operand B Operand B Operand A Operand B Operand A Operand B Single Multiplier x M loops x Multiplier 0 Multiplier 1 x (k adds) x + Output m/k loops Multiplier k Accumulator Function implemented in General purpose DSP m/k accumulate Function implemented in LatticeECP2/M sysDSP Block Capabilities The sysDSP block in the LatticeECP2/M family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeECP2/M family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. In the LatticeECP2/ M family the DSP elements can be concatenated. The resources in each sysDSP block can be configured to support the following four elements: 2-21 Lattice Semiconductor * MULT (Multiply) * MAC (Multiply, Accumulate) * MULTADDSUB (Multiply, Addition/Subtraction) * MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate) Architecture LatticeECP2/M Family Data Sheet The number of elements available on each block depends in the width selected from the three available options x9, x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions. Table 2-7 shows the capabilities of the block. Table 2-7. Maximum Number of Elements in a Block Width of Multiply MULT MAC MULTADDSUB MULTADDSUBSUM x9 8 2 4 2 x18 4 2 2 1 x36 1 -- -- -- Some options are available in four elements. The input register in all the elements can be directly loaded or can be loaded as a shift register from previous operand registers. By selecting "dynamic operation" the following operations are possible: * In the `Signed/Unsigned' options the operands can be switched between signed and unsigned on every cycle. * In the `Add/Sub' option the Accumulator can be switched between addition and subtraction on every cycle. * The loading of operands can switch between parallel and serial operations. 2-22 Lattice Semiconductor MULT sysDSP Element Architecture LatticeECP2/M Family Data Sheet This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-23 shows the MULT sysDSP element. Figure 2-23. MULT sysDSP Element Shift Register B In Multiplicand m Shift Register A In m m Multiplier n n n Output Register Input Data Register A m Multiplier Input Data Register B m n n x Pipeline Register m+n (default) m+n Output Signed A Signed B Input Register Input Register To Multiplier To Multiplier CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Shift Register B Out Shift Register A Out 2-23 Lattice Semiconductor MAC sysDSP Element Architecture LatticeECP2/M Family Data Sheet In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but the output register is always enabled. The output register is used to store the accumulated value. The Accumulators in the DSP blocks in the LatticeECP2/M family can be initialized dynamically. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-24 shows the MAC sysDSP element. Figure 2-24. MAC sysDSP Serial Register B in Multiplicand m Serial Register A in m Accumulator Preload n Input Data Register A m Multiplier Input Data Register B n n n Signed A Signed B Addn Accumsload Input Register Input Register Input Register Input Register Pipeline Register Pipeline Register Pipeline Register Pipeline Register Output Register m+n (default) Pipeline Register x Output Register Multiplier n n m m+n+16 (default) Output m+n+16 (default) To Accumulator To Accumulator To Accumulator Overflow signal CLK (CLK0,CLK1,CLK2,CLK3) To Accumulator CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) SROB SROA 2-24 Lattice Semiconductor MULTADDSUB sysDSP Element Architecture LatticeECP2/M Family Data Sheet In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-25 shows the MULTADDSUB sysDSP element. Figure 2-25. MULTADDSUB Shift Register B In Multiplicand A0 n n Input Data Register B n m m Input Data Register A m Multiplier Shift Register A In m CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) Multiplier B0 RST(RST0,RST1,RST2,RST3) n n m m m x Pipeline Register m+n (default) Add/Sub Multiplicand A1 Output Register Output m+n+1 (default) Multiplier B1 n n m+n+1 (default) m Multiplier m+n (default) Input Data Register A Input Data Register B n m Pipeline Pipe Register Reg Pipeline Pipe Register Reg Pipeline Pipe Register Reg x Pipeline Register Signed A Signed B Addn n Input Register Input Register Input Register To Add/Sub To Add/Sub To Add/Sub Shift Register B Out Shift Register A Out 2-25 Lattice Semiconductor MULTADDSUBSUM sysDSP Element Architecture LatticeECP2/M Family Data Sheet In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-26 shows the MULTADDSUBSUM sysDSP element. Figure 2-26. MULTADDSUBSUM Shift Register B In Multiplicand A0 Multiplier B0 n n Input Data Register B n m m Input Data Register A m Multiplier Shift Register A In m CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) n m m m Input Data Register A n x Pipeline Register m+n (default) RST(RST0,RST1,RST2,RST3) Add/Sub0 Multiplicand A1 Multiplier B1 n m+n (default) Multiplier n n Input Data Register B n x Pipeline Register m+n+1 SUM Output Register Multiplicand A2 Multiplier B2 n n Input Data Register B m m m m+n+2 Output m+n+2 n Input Data Register A m Multiplier n m m m Input Data Register A m x Pipeline Register m+n (default) m+n+1 Add/Sub1 Multiplicand A3 Multiplier B3 n m+n (default) Multiplier n n Input Data Register B n m Input Register Input Register Input Register Input Register Pipeline Register Pipeline Register Pipeline Register Pipeline Register x Pipeline Register Signed A Signed B Addn0 Addn1 n To Add/Sub0, Add/Sub1 To Add/Sub0, Add/Sub1 To Add/Sub0 To Add/Sub1 Shift Register B Out Shift Register A Out Clock, Clock Enable and Reset Resources Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3) 2-26 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. Signed and Unsigned with Different Widths The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two's complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36 width is reached. Table 2-8 provides an example of this. Table 2-8. Sign Extension Example Number +5 -6 Unsigned 0101 N/A Unsigned 9-bit 000000101 N/A Unsigned 18-bit 000000000000000101 N/A Signed 0101 1010 Two's Complement Signed 9 Bits 000000101 111111010 Two's Complement Signed 18 Bits 000000000000000101 111111111111111010 OVERFLOW Flag from MAC The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two unsigned numbers are added and the result is a smaller number than the accumulator, "roll-over" is said to have occurred and an overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative numbers are added with a positive sum, then the accumulator "roll-over" is said to have occurred and an overflow signal is indicated. Note that when overflow occurs the overflow flag is present for only one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signals for signed and unsigned operands are listed in Figure 2-27. Figure 2-27. Accumulator Overflow/Underflow 0101111100 0101111101 0101111110 0101111111 1010000000 1010000001 1010000010 252 253 254 255 256 257 258 000000011 000000010 000000001 000000000 111111111 111111110 111111101 3 2 1 0 511 510 509 Carry signal is generated for one cycle when this boundary is crossed Unsigned Operation 0101111100 252 Overflow signal is generated 0101111101 253 0101111110 254 for one cycle when this 0101111111 255 boundary is crossed 1010000000 -256 1010000001 -255 1010000010 -254 000000011 000000010 000000001 000000000 111111111 111111110 111111101 +3 +2 +1 0 -1 -2 -3 Signed Operation 2-27 Lattice Semiconductor IPexpressTM Architecture LatticeECP2/M Family Data Sheet The user can access the sysDSP block via the ispLEVER IPexpress tool, which provides the option to configure each DSP module (or group of modules) or by direct HDL instantiation. In addition, Lattice has partnered with The MathWorks(R) to support instantiation in the Simulink(R) tool, a graphical simulation environment. Simulink works with ispLEVER to dramatically shorten the DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeECP2/M DSP include the Bit Correlator, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores. Resources Available in the LatticeECP2/M Family Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP2/M family. Table 2-10 shows the maximum available EBR RAM Blocks in each LatticeECP2/M device. EBR blocks, together with Distributed RAM can be used to store variables locally for fast DSP operations. Table 2-9. Maximum Number of DSP Blocks in the LatticeECP2/M Family Device ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 DSP Block 3 6 7 8 18 22 6 8 22 24 42 9x9 Multiplier 24 48 56 64 144 176 48 64 176 192 336 18x18 Multiplier 12 24 28 32 72 88 24 32 88 96 168 36x36 Multiplier 3 6 7 8 18 22 6 8 22 24 42 Table 2-10. Embedded SRAM in the LatticeECP2/M Family Device ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 EBR SRAM Block 3 12 15 18 21 60 66 114 225 246 288 Total EBR SRAM (Kbits) 55 221 277 332 387 1106 1217 2101 4147 4534 5308 2-28 Lattice Semiconductor LatticeECP2/M DSP Performance Architecture LatticeECP2/M Family Data Sheet Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of the LatticeECP2/M family. Table 2-11. DSP Performance Device ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 DSP Block 3 6 7 8 18 22 6 8 22 24 42 DSP Performance GMAC 3.9 7.8 9.1 10.4 23.4 28.6 7.8 10.4 28.6 31.2 54.6 For further information about the sysDSP block, please see the list of additional technical information at the end of this data sheet. Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the buffer. Table 2-12 provides the PIO signal list. 2-29 Lattice Semiconductor Figure 2-28. PIC Diagram PIOA Architecture LatticeECP2/M Family Data Sheet TD OPOS1 ONEG1 IOLT0 Tristate Register Block OPOS0 OPOS2* ONEG0 ONEG2* PADA "T" IOLD0 Output Register Block sysIO Buffer QNEG0* QNEG1* QPOS0* QPOS1* INCK** INDD INFF IPOS0 IPOS1 CLK CE LSR GSRN ECLK1 ECLK2 DDRCLKPOL* DQSXFER* Control Muxes CLK1 CEO LSR GSR CLK0 CEI Input Register Block DI PADB "C" PIOB *Signals are available on left/right/bottom edges only. ** Selected blocks. Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as "T" and "C") as shown in Figure 2-28. The PAD Labels "T" and "C" distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs. 2-30 Lattice Semiconductor Table 2-12. PIO Signals List Name CE0, CE1 CLK0, CLK1 ECLK1, ECLK2 LSR GSRN INCK2 DQS INDD INFF IPOS0, IPOS1 QPOS0 , QPOS1 1 1 Architecture LatticeECP2/M Family Data Sheet Type Control from the core Control from the core Control from the core Control from the core Control from routing Input to the core Input to PIO Input to the core Input to the core Input to the core Input to the core Input to the core Output data from the core Tristate control from the core Control from the core Tristate control from the core Control from core Description Clock enables for input and output block flip-flops System clocks for input and output blocks Fast edge clocks Local Set/Reset Global Set/Reset (active low) Input to Primary Clock Network or PLL reference inputs DQS signal from logic (routing) to PIO Unregistered data input to core Registered input on positive edge of the clock (CLK0) Double data rate registered inputs to the core Gearbox pipelined inputs to the core Gearbox pipelined inputs to the core Output signals from the core for SDR and DDR operation Signals to Tristate Register block for DDR operation Dynamic input delay control bits Tristate signal from the core used in SDR operation Controls signal to the Output block QNEG01, QNEG11 OPOS0, ONEG0, OPOS2, ONEG2 OPOS1 ONEG1 DEL[3:0] TD DDRCLKPOL DQSXFER Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block 1. Signals available on left/right/bottom only. 2. Selected I/O. PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Input Register Block The input register blocks for PIOs in left, right and bottom edges contain delay elements and registers that can be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous interfaces, before they are passed to the device core. Figure 2-29 shows the diagram of the input register block for left, right and bottom edges. The input register block for the top edge contains one memory element to register the input signal as shown in Figure 2-30. The following description applies to the input register block for PIOs in the left, right and bottom edges of the device. Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and, in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows three modes of operation. In the single data rate (SDR) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. In DDR Mode, two registers are used to sample the data on the positive and negative edges of the DQS signal, creating two data streams, D0 and D1. These two data streams are synchronized with the system clock before entering the core. Further discussion on this topic is in the DDR Memory section of this data sheet. 2-31 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet By combining input blocks of the complementary PIOs and sharing some registers from output blocks, a gearbox function can be implemented, which takes a double data rate signal applied to PIOA and converts it as four data streams, IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-29 shows the diagram using this gearbox function. For more information about this topic, please see information regarding additional documentation at the end of this data sheet. The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred from the DQS to the system clock domain. For further information about this topic, see the DDR Memory section of this data sheet. Figure 2-29. Input Register Block for Left, Right and Bottom Edges DI (From sysIO Buffer) Fixed Delay Dynamic Delay 0 0 1 INCK** To DQS Delay Block** INDD DDR Registers SDR & Sync Registers Clock Transfer Registers IPOS0A D Q QPOS0A D0 D Q D Q 1 DEL [3:0] D-Type /LATCH D-Type* D-Type From Routing D Q D1 D Q D2 D Q D Q IPOS1A QPOS1A Delayed DQS 0 1 D-Type D-Type D-Type /LATCH D-Type* To Routing CLK0 (of PIO A) DDRCLKPOL CLKA True PIO (A) in LVDS I/O Pair Comp PIO (B) in LVDS I/O Pair DI (From sysIO Buffer) DDRSRC DDR Registers 0 1 INCK** To DQS Delay Block** INDD SDR & Sync Registers 0 1 Fixed Delay Dynamic Delay 0 Clock Transfer Registers D0 IPOS0B QPOS0B D Q 1 D Q DEL [3:0] D-Type D-Type /LATCH D Q D-Type* From Routing Delayed DQS 0 1 IPOS1B D Q D1 0 D Q D2 1 D Q D Q QPOS1B D-Type D-Type D-Type /LATCH D-Type* To Routing CLK0 (of PIO B) DDRCLKPOL CLKB *Shared with output register **Selected PIO. Gearbox Configuration Bit Note: Simplified version does not show CE and SET/RESET details 2-32 Lattice Semiconductor Figure 2-30. Input Register Block Top Edge Architecture LatticeECP2/M Family Data Sheet INDD Fixed Delay Dynamic Delay D Q D-Type /LATCH IPOS0 DEL[3:0] CLK0 (from routing) Note: Simplified version does not show CE and SET/RESET details. *On selected blocks. Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysI/O buffers. The blocks on the PIOs on the left, right and bottom contain a register for SDR operation that is combined with an additional latch for DDR operation. Figure 2-31 shows the diagram of the Output Register Block for PIOs on the left, right and the bottom edges. Figure 2-32 shows the diagram of the Output Register Block for PIOs on the top edge of the device. In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a Dtype or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. Then at the next clock cycle this registered OPOS0 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). By combining the output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox function can be implemented, that takes four data streams: ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-32 shows the diagram using this gearbox function. For more information about this topic, please see information regarding additional documentation at the end of this data sheet. 2-33 To Routing DI (from sysIO buffer) INCK* Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges TD Tristate Logic ONEG1 D Q D-Type /LATCH 0 1 0 0 1 TO OPOS1 D Q D Q Latch 1 D-Type To sysIO Buffer From Routing 0 ONEG0 D Q 0 1 D-Type* 1 D Q D-Type /LATCH DDR Output Registers DO 0 0 1 OPOS0 Q D D-Type* Q D Latch 0 D 0 1 1 Q D Latch Q 1 D-Type CLKA ECLK1 ECLK2 CLK1 (CLKA) DQSXFER Clock Transfer Registers 0 1 0 1 Programmable Control Output Logic True PIO (A) in LVDS I/O Pair Comp PIO (B) in LVDS I/O Pair TD Tristate Logic ONEG1 Q D D-Type /LATCH 0 1 0 0 1 TO OPOS1 D Q D Q Latch 1 D-Type To sysIO Buffer From Routing ONEG0 D Q D-Type* Q D D-Type /LATCH DDR Output Registers 0 1 DO 0 OPOS0 D Q D Latch Q D Q D Latch Q 1 D-Type* D-Type CLKB ECLK1 ECLK2 CLK1 (CLKB) DQSXFER Clock Transfer Registers 0 1 0 1 Programmable Control Output Logic * Shared with input register Note: Simplified version does not show CE and SET/RESET details 2-34 Lattice Semiconductor Figure 2-32. Output and Tristate Block, Top Edge TD Architecture LatticeECP2/M Family Data Sheet 0 1 0 TO ONEG1 Q D D-Type /LATCH 1 To sysIO Buffer From Routing Tristate Logic ONEG0 DO 0 ECLK1 ECLK2 CLK1 (CLKA) 0 Q D D-Type /LATCH 1 Output Logic 1 Note: Simplified version does not show CE and SET/RESET details. Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block with the Output Block for the left, right and bottom edges and Figure 2-32 shows the diagram of the Tristate Register Block with the Output Block for the top edge. In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a Dtype or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct register for feeding to the output (D0). Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is selected from one of the clock signals provided from the general purpose routing, one of the edge clocks (ECLK1/ ECLK2) and a DQS signal provided from the programmable DQS pin and provided to the input register block. The clock can optionally be inverted. DDR Memory Support Certain PICs have additional circuitry to allow the implementation of high speed source synchronous and DDR memory interfaces. The support varies by the edge of the device as detailed below. Left and Right Edges PICs on these edges have registered elements that support DDR memory interfaces. One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the set of 16 PIOs. Figure 2-33 shows the assignment of DQS pins in each set of 16 PIOs. Bottom Edge PICs on the bottom edge have registered elements that support DDR memory interfaces. One of every 18 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus that spans the set of 18 PIOs. Figure 2-34 shows the assignment of DQS pins in each set of 18 PIOs. 2-35 Lattice Semiconductor Top Edge Architecture LatticeECP2/M Family Data Sheet The PICs on the top edge are different from PIOs on the left, right and bottom edges. PIOs on this edge do not have DDR registers or DQS signals. The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Additional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. Interfaces on the left and right edges are designed for DDR memories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits of data. Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A DQS PIO B PIO A PIO B PIO A PIO B PIO A PIO B sysIO Buffer Delay PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" Assigned DQS Pin PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" 2-36 Lattice Semiconductor Figure 2-34. DQS Input Routing for the Bottom Edge of the Device PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A Architecture LatticeECP2/M Family Data Sheet PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" sysIO Buffer Delay Assigned DQS Pin DQS PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" DLL Calibrated DQS Delay Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock (referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces. The DQS signal (selected PIOs only, as shown in Figure 2-35) feeds from the PAD through a DQS delay element to a dedicated DQS routing resource. The DQS signal also feeds polarity control logic, which controls the polarity of the clock to the sync registers in the input register blocks. Figure 2-35 and Figure 2-36 show how the DQS transition signals are routed to the PIOs. The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration (6-bit bus) signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates DQS delays in its half of the device as shown in Figure 2-35. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. 2-37 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution I/O Bank 0 I/O Bank 1 Spans 16 PIOs ECLK1 I/O B a n k 7 DDR_DLL (Left) DDR_DLL (Right) I/O B a n k 2 ECLK2 DQS Input Delayed DQS Polarity Control I/O B a n k 6 I/O B a n k 3 DQSXFER DQS Delay Control Bus Spans 18 PIOs I/O Bank 5 Note: Bank 8 is not shown. I/O Bank 4 2-38 Lattice Semiconductor Figure 2-36. DQS Local Bus CLK1 ECLK2 ECLK1 Polarity control Architecture LatticeECP2/M Family Data Sheet DCNTL[6:0] DQSXFER DQS PIO DQSXFER Output Register Block Input Register Block GSR CEI DQS CLK1 DQS To DDR Reg. sysIO Buffer DDR Datain PAD To Sync Reg. DI PIO Polarity Control Logic DQS DQSDEL Calibration bus from DLL DCNTL[6:0] sysIO Buffer DQS Strobe PAD DI ECLK1 DQSXFER DQSXFERDEL* DCNTL[6:0] *DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO. Polarity Control Logic In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used. This changes the edge on which the data is registered in the synchronizing registers in the input register block. This requires evaluation at the start of each READ cycle for the correct clock polarity. Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit detects the first DQS rising edge after the preamble state. This signal is used to control the polarity of the clock to the synchronizing registers. 2-39 Lattice Semiconductor DQSXFER Architecture LatticeECP2/M Family Data Sheet LatticeECP2/M devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories that require DQS strobe be shifted 90o. This shifted DQS strobe is generated by the DQSDEL block. The DQSXFER signal runs the span of the data bus. sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety of standards that are found in today's systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysI/O Buffer Banks LatticeECP2/M devices have nine sysI/O buffer banks: eight banks for user I/Os arranged two per side. The ninth sysI/O buffer bank (Bank 8) is located adjacent to Bank 3 and has dedicated/shared I/Os for configuration. When a shared pin is not used for configuration it is available as a user I/O. Each bank is capable of supporting multiple I/O standards. Each sysI/O bank has its own I/O supply voltage (VCCIO). In addition, each bank, except Bank 8, has voltage references, VREF1 and VREF2, which allow it to be completely independent from the others. Bank 8 shares two voltage references, VREF1 and VREF2, with Bank 3. Figure 2-37 shows the nine banks and their associated supplies. In LatticeECP2/M devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs independent of VCCIO. Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the referenced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin. Each I/O is individually configurable based on the bank's supply and reference voltages. 2-40 Lattice Semiconductor Figure 2-37. LatticeECP2 Banks TOP VREF1(0) VCCIO0 V REF1(1) VCCIO1 Architecture LatticeECP2/M Family Data Sheet GND VREF2(1) Bank 0 V CCIO7 GND VREF2(0) Bank 1 V CCIO2 V REF1(2) V REF2(2) GND Bank 2 V REF1(7) V REF2(7) LEFT GND Bank 7 RIGHT V CCIO3 V REF1(3) V REF2(3) GND V CCIO8 GND Bank 3 V CCIO6 V REF1(6) V REF2(6) GND Bank 5 Bank 4 Bank 6 Bank 8 VCCIO5 VREF1(5) VREF2(5) VCCIO4 VREF1(4) VREF2(4) GND BOTTOM 2-41 GND Lattice Semiconductor Figure 2-38. LatticeECP2M Banks TOP VREF1(0) VCCIO0 SERDES Quad Architecture LatticeECP2/M Family Data Sheet GND VREF2(1) V REF1(1) VCCIO1 SERDES Quad Bank 0 V CCIO7 V REF1(7) V REF2(7) GND GND VREF2(0) Bank 1 VCCIO2 VREF1(2) V REF2(2) GND Bank 2 Bank 7 RIGHT LEFT VCCIO3 V REF1(3) V REF2(3) GND Bank 3 V CCIO6 V REF2(6) GND Bank 6 V REF1(6) Bank 8 VCCIO8 GND Bank 5 Bank 4 SERDES Quad SERDES Quad VCCIO5 VREF1(5) VREF2(5) GND BOTTOM LatticeECP2/M devices contain two types of sysI/O buffer pairs. 1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 2. Bottom (Bank 4 and Bank 5) sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two 2-42 VCCIO4 VREF1(4) VREF2(4) GND Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 3. Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Outputs) The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks. 4. Bank 8 sysI/O Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by Configuration) The sysI/O buffers in Bank 8 consist of single-ended output drivers and single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be configured as a differential input. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. In LatticeECP2 devices, only the I/Os on the bottom banks have programmable PCI clamps. In LatticeECP2M devices, the I/Os on the left and bottom banks have programmable PCI clamps. Typical sysI/O I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user's responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in LatticeECP2/M devices, see the list of additional technical documentation at the end of this data sheet. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. Supported sysI/O Standards The LatticeECP2/M sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V, 1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/ O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional technical information at the end of this data sheet. 2-43 Lattice Semiconductor Table 2-13. Supported Input Standards Input Standard Single Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI 33 HSTL18 Class I, II HSTL15 Class I SSTL3 Class I, II SSTL2 Class I, II SSTL18 Class I, II Differential Interfaces Differential SSTL18 Class I, II Differential SSTL2 Class I, II Differential SSTL3 Class I, II Differential HSTL15 Class I Differential HSTL18 Class I, II LVDS, MLVDS, LVPECL, BLVDS, RSDS -- -- -- -- -- -- -- -- -- -- -- -- -- 0.9 0.75 1.5 1.25 0.9 VREF (Nom.) Architecture LatticeECP2/M Family Data Sheet VCCIO1 (Nom.) -- -- -- 1.8 1.5 -- 3.3 -- -- -- -- -- -- -- -- -- -- -- 1 When not specified, VCCIO can be set anywhere in the valid operating range (page 3-1). 2-44 Lattice Semiconductor Table 2-14. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II HSTL15 Class I SSTL3 Class I, II SSTL2 Class I, II SSTL18 Class I, II Differential Interfaces Differential SSTL3, Class I, II Differential SSTL2, Class I, II Differential SSTL18, Class I, II Differential HSTL18, Class I, II Differential HSTL15, Class I LVDS MLVDS1 BLVDS1 LVPECL1 RSDS 1 Architecture LatticeECP2/M Family Data Sheet Drive 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA, 16mA, 20mA 4mA, 8mA, 12mA, 16mA 4mA, 8mA 2mA, 6mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA, 20mA 4mA, 8mA, 12mA 16mA 4mA, 8mA 2mA, 6mA N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4mA, 8mA, 12mA, 16mA, 20mA VCCIO (Nom.) 3.3 3.3 2.5 1.8 1.5 1.2 -- -- -- -- -- 3.3 1.8 1.5 3.3 2.5 1.8 3.3 2.5 1.8 1.8 1.5 2.5 2.5 2.5 3.3 2.5 3.3 LVCMOS33D1 1. Emulated with external resistors. For more detail, please see information regarding additional technical documentation at the end of this data sheet. Hot Socketing LatticeECP2/M devices have been carefully designed to ensure predictable behavior during power-up and powerdown. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. This allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many multiple power supply and hot-swap applications. 2-45 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet SERDES and PCS (Physical Coding Sublayer) LatticeECP2M devices feature up to 16 channels of embedded SERDES arranged in quads at the corners of the devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices. Each quad contains four dedicated SERDES (Ch0 to Ch3) for high-speed, full-duplex serial data transfer. Each quad also has a PCS block that interfaces to the SERDES channels and contains digital logic to support an array of popular data protocols. PCS also contains logic to the interface to FPGA core. Figure 2-39. SERDES Quads (LatticeECP2M70/LatticeECP2M100) ULC SERDES Quad Ch 3 Ch 2 Ch 1 Ch 0 URC SERDES Quad Ch 3 Ch 2 Ch 1 Ch 0 PCS Digital Logic PCS Digital Logic PCS Digital Logic Ch 3 Ch 2 Ch 1 Ch 0 Ch 3 PCS Digital Logic Ch 2 Ch 1 Ch 0 LLC SERDES Quad LRC SERDES Quad Table 2-15. Available SERDES Quads per LatticeECP2M Devices Device ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 URC Quad Available Available Available Available Available ULC Quad -- -- -- Available Available LRC Quad -- -- Available Available Available LLC Quad -- -- -- Available Available SERDES Block A differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and de-serializes the data-stream before passing the 8- or 10-bit data to the PCS logic. The transmit channel receives the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differential buffers. There is a single transmit clock per quad. Figure 2-40 shows a single channel SERDES and its interface to the PCS logic. Each SERDES receiver channel provides a recovered clock to the PCS block and to the FPGA core logic. 2-46 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet Each Transmit and Receive channel has its independent power supplies. The Output and Input buffers of each channel also have their own independent power supplies. In addition, there are separate power supplies for PLL, terminating resistor per quad. Figure 2-40. Simplified Channel Block Diagram for SERDES and PCS SERDES (Analog) RX REFCLK Receiver PCS (Digital) Recovered Clock Elastic Buffer Read Clock Equalizer Deserializer 1:8/1:10 Polarity Adjust Byte Boundary Detect, 8b/10b Decoder CTC FIFO Down Sample FIFO 16/20 bits Receive Data FPGA Receive Clock TX REFCLK TX PLL To FPGA Core FPGA Transmit Clock Serializer 8:1/10:1 Polarity Adjust 8b/10b Encoder Up Sample FIFO Transmit 8/10 bits or 16/20 bits Transmit Data From Transmit PLL (In Common Block) PCS As shown in Figure 2-40, the PCS receives the parallel digital data from the deserializer receivers and adjusts the polarity, detects, byte boundary, decodes (8b/10b) and provides Clock Tolerance Compensation (CTC) FIFO for changing the clock domain from receiver clock to the FPGA Clock. For the transmit channel, the PCS block receives the parallel data from the FPGA core, encodes it with 8b/10b, adjusts the polarity and passes the 8/10 bit data to the transmit SERDES channel. The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic. The PCS interface to FPGA can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. SCI (SERDES Client Interface) Bus The SERDES Client Interface (SCI) is a soft IP interface that allow the SERDES/PCS Quad block to be controlled by registers as opposed to the configuration memory cells. It is a simple register configuration interface. The ispLEVER design tools from Lattice support all modes of the PCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow users to define their own operation. With ispLEVER, the user can define the mode for each quad in a design. Popular standards such as 10Gb Ethernet and x4 PCI-Express and 4x Serial RapidIO can be implemented using IP (provided by Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the core. For further information about SERDES, please see the list of additional technical documentation at the end of this data sheet. 2-47 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet IEEE 1149.1-Compliant Boundary Scan Testability All LatticeECP2/M devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. Device Configuration All LatticeECP2/M devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration, and the sysCONFIG port, support both byte-wide and serial configuration, including the standard SPI Flash interface. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In- System Configuration specification. The sysCONFIG port is a 20-pin interface with six I/Os used as dedicated pins with the remainder used as dual-use pins. See Lattice technical note number TN1108, LatticeECP2 sysCONFIG Usage Guide for more information about using the dual-use pins as general purpose I/Os. On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. Enhanced Configuration Option LatticeECP2/M devices have enhanced configuration features such as: decryption support, TransFRTM I/O and dual boot image support. 1. Decryption Support LatticeECP2/M devices provide on-chip, One Time Programmable (OTP) non-volatile key storage to support decryption of a 128-bit AES encrypted bitstream, securing designs and deterring design piracy. 2. TransFR (Transparent Field Reconfiguration) TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM(R) command. TransFR I/O allows I/O states to be frozen during device configuration. This allows the device to be field updated with a minimum of system disruption and downtime. See Lattice technical note number TN1087, Minimizing System Interruption During Configuration Using TransFR Technology, for details. 3. Dual Boot Image Support Dual boot images are supported for applications requiring reliable remote updates of configuration data for the system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the LatticeECP2/M can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the LatticeECP2/M device can revert back to the original backup configuration and try again. This all can be done without power cycling the system. For more information about device configuration, please see the list of additional technical documentation at the end of this data sheet. Software Error Detect (SED) Support LatticeECP2/M devices have dedicated logic to perform CRC checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, the LatticeECP2 device can also be programmed 2-48 Lattice Semiconductor Architecture LatticeECP2/M Family Data Sheet for checking soft errors (SED) in SRAM. This SED operation can be run in the background during user mode. If a soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a known good boot image or generate an error signal. For further information about Soft Error Detect (SED) support, please see the list of additional technical documentation at the end of this data sheet. External Resistor LatticeECP2/M devices require a single external, 10K ohm 1% value between the XRES pin and ground. Device configuration will not be completed if this resistor is missing. There is no boundary scan register on the external resistor pad. On-Chip Oscillator Every LatticeECP2/M device has an internal CMOS oscillator which is used to derive a Master Clock for configuration. The oscillator and the Master Clock run continuously and are available to user logic after configuration is completed. The software default value of the Master Clock is 2.5MHz. Table 2-16 lists all the available Master Configuration Clock frequencies for normal non-encrypted mode and encrypted mode. When a different Master Clock is selected during the design process, the following sequence takes place: 1. Device powers up with a Master Clock frequency of 3.1MHz. 2. During configuration, users select a different master clock frequency. 3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received. 4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the Master Clock frequency of 2.5MHz. This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further information about the use of this oscillator for configuration or user mode, please see the list of additional technical documentation at the end of this data sheet. Table 2-16. Selectable Master Clock (CCLK) Frequencies During Configuration Non-Encrypted Mode CCLK (MHz) 2.5 1 Encrypted Mode CCLK (MHz) 2.51 5.4 10.0 34.0 41.0 45.0 -- 13.0 15.0 20.0 26.0 30.0 34.0 41.0 45.0 55.0 60.0 -- -- -- 130.0 4.3 5.4 6.9 8.1 9.2 10.0 1. Software default frequency. Density Shifting The LatticeECP2/M family is designed to ensure that different density devices in the same family and in the same package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likelihood of success in each case. Design migration between LatticeECP2 and LatticeECP2M families is not possible. For specific requirements relating to sysCONFIG pins of the ECP2M50, M70 and M100, see the Logic Signal Connections tables. 2-49 LatticeECP2/M Family Data Sheet DC and Switching Characteristics February 2008 Data Sheet DS1006 Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V Input or I/O Tristate Voltage Applied4 . . . . . . -0.5 to 3.75V Storage Temperature (Ambient) . . . . . . . . . -65 to 150C Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125C 1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns. Recommended Operating Conditions Symbol VCC 1, 4, 5 Parameter Core Supply Voltage Auxiliary Supply Voltage PLL Supply Voltage I/O Driver Supply Voltage Supply Voltage for IEEE 1149.1 Test Access Port Junction Temperature, Commercial Operation Junction Temperature, Industrial Operation Input Buffer Power Supply (1.2V) Input Buffer Power Supply (1.5V) Output Buffer Power Supply (1.2V) Output Buffer Power Supply (1.5V) Termination Resistor Switching Power Supply Receive Power Supply Transmit Power Supply PLL and Reference Clock Buffer Power Min. 1.14 3.135 1.14 1.14 1.14 0 -40 1.14 1.425 1.14 1.425 3.135 1.14 1.14 1.14 Max. 1.26 3.465 1.26 3.465 3.465 85 100 1.26 1.575 1.26 1.575 3.465 1.26 1.26 1.26 Units V V V V V C C V V V V V V V V VCCAUX1, 3, 4, 5 VCCPLL VCCIO1, 2, 4 VCCJ tJIND 1 tJCOM SERDES External Power Supply (For LatticeECP2M Family Only) VCCIB VCCOB VCCAUX33 VCCRX6 VCCTX6 VCCP6 1. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be connected to the same power supply as VCCAUX. VCC and VCCPLL must be connected to the same power supply. 2. See recommended voltages by I/O standard in subsequent table. 3. VCCAUX ramp rate must not exceed 30mV/s during power-up when transitioning between 0V and 3.3V. 4. For proper power-up configuration, users must ensure that the configuration control signals such as the CFGx, INITN, PROGRAMN and DONE pins are driven to the proper logic levels when the device powers up. The device power-up is triggered by the last of V CC, VCCAUX or VCCIO8 supplies that reaches its minimum valid levels. Alternatively, if the configuration control signals are pulled up by V CCIO8, the VCCIO8 (configuration I/O bank) voltage must be powered up prior to or at the same time as the last of VCC or VCCAUX reaches its minimum levels. 5. For power-up, VCC must reach its valid minimum value before powering up VCCAUX (LatticeECP2/M "S" version devices only). 6. VCCRX,VCCTX and VCCP must be tied together in each quad and all quads need to be powered up. (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DS1006 DC and Switching_01.7 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet Hot Socketing Specifications1, 2, 3, 4 Symbol IDK IHDIN5 Parameter Input or I/O leakage current SERDES average input current when device is powered down and inputs are driven Condition 0 VIN VIH (MAX.) Min. -- -- Typ. -- -- Max. +/-1000 4 Units A mA 1. VCC, VCCAUX and VCCIO should rise/fall monotonically. VCC and VCCPLL must be connected to the same power supply (applies to ECP2-6, ECP2-12 and ECP2-20 only). 2. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX) or 0 VCCAUX VCCAUX (MAX). 3. IDK is additive to IPU, IPW or IBH. 4. LVCMOS and LVTTL only. 5. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed VCCIB of 1.575V, 8b10b data and internal AC coupling. 3-2 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH IIH1 IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT C1 C2 1 Parameter Input or I/O Low Leakage Input or I/O High Leakage I/O Active Pull-up Current I/O Active Pull-down Current Condition 0 VIN (VCCIO - 0.2V) (VCCIO - 0.2V) < VIN 3.6V 0 VIN 0.7 VCCIO VIL (MAX) VIN VIH (MAX) Min. -- -- -30 30 30 -30 -- -- VIL (MAX) -- -- Typ. -- -- -- -- -- -- -- -- -- 8 6 Max. 10 150 -210 210 -- -- 210 -210 VIH (MIN) -- -- Units A A A A A A A A V pf pf Bus Hold Low Sustaining Current VIN = VIL (MAX) Bus Hold High Sustaining Current VIN = 0.7 VCCIO Bus Hold Low Overdrive Current 0 VIN VCCIO Bus Hold High Overdrive Current 0 VIN VCCIO Bus Hold Trip Points I/O Capacitance 2 0 VIN VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) Dedicated Input Capacitance2 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25oC, f = 1.0MHz. 3-3 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2 Supply Current (Standby)1, 2, 3, 4 Over Recommended Operating Conditions Symbol Parameter ECP2-6 ECP2-12 ICC Core Power Supply Current ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ICCAUX Auxiliary Power Supply Current ECP2-20 ECP2-35 ECP2-50 ECP2-70 ICCGPLL ICCSPLL GPLL Power Supply Current (per GPLL) GPLL Power Supply Current (per SPLL) ECP2-35, -50, -70 Only ECP2-35, -50, -70 Only ECP2-6 ECP2-12 ICCIO Bank Power Supply Current (Per Bank) ECP2-20 ECP2-35 ECP2-50 ECP2-70 ICCJ 1. 2. 3. 4. 5. Device Typ.5 10 20 30 50 70 100 24 24 24 24 24 24 0.5 0.5 2 2 2 2 2 2 3 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA VCCJ Power Supply Current All Devices For further information about supply current, please see the list of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Pattern represents a "blank" configuration data file. TJ = 25C, power supplies at normal voltage. 3-4 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2M Supply Current (Standby)1, 2, 3, 4 Over Recommended Operating Conditions Symbol Parameter Device ECP2M20 ECP2M35 ICC Core Power Supply Current ECP2M50 ECP2M70 ECP2M100 ECP2M20 ECP2M35 ICCAUX Auxiliary Power Supply Current ECP2M50 ECP2M70 ECP2M100 ICCGPLL ICCSPLL GPLL Power Supply Current (per GPLL) GPLL Power Supply Current (per SPLL) All Devices All Devices ECP2M20 ECP2M35 ICCIO Bank Power Supply Current (Per Bank) ECP2M50 ECP2M70 ECP2M100 ICCJ 1. 2. 3. 4. 5. Typ.5 25 50 85 100 100 24 24 24 24 24 0.5 0.5 2 2 2 2 2 3 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA VCCJ Power Supply Current All Devices For further information about supply current, please see the list of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Pattern represents a "blank" configuration data file. TJ = 25C, power supplies at normal voltage. 3-5 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2 Initialization Supply Current1, 2, 3, 4 Over Recommended Operating Conditions Symbol Parameter ECP2-6 ECP2-12 ICC Core Power Supply Current ECP2-20 ECP2-35 ECP2-50 ECP2-70 ECP2-6 ECP2-12 ICCAUX Auxiliary Power Supply Current ECP2-20 ECP2-35 ECP2-50 ECP2-70 ICCGPLL ICCSPLL ICCIO ICCJ 1. 2. 3. 4. 5. 6. Device Typ.5, 6 34 54 82 135 187 267 30 30 30 30 30 30 0.5 0.5 3 4 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA GPLL Power Supply Current (per GPLL) SPLL Power Supply Current (per SPLL) Bank Power Supply Current (per Bank) VCCJ Power Supply Current ECP2-35, -50, -70 Only ECP2-35, -50, -70 Only All Devices All Devices Until DONE signal is active. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. TJ = 25oC, power supplies at nominal voltage. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O configuration. 3-6 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2M Initialization Supply Current1, 2, 3, 4 Over Recommended Operating Conditions Symbol Parameter Device ECP2M20 ECP2M35 ICC Core Power Supply Current ECP2M50 ECP2M70 ECP2M100 ECP2M20 ECP2M35 ICCAUX Auxiliary Power Supply Current ECP2M50 ECP2M70 ECP2M100 ICCGPLL ICCSPLL ICCIO ICCJ 1. 2. 3. 4. 5. 6. Typ.5, 6 41 107 169 254 378 30 30 30 30 30 0.5 0.5 3 4 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA GPLL Power Supply Current (per GPLL) SPLL Power Supply Current (per SPLL) Bank Power Supply Current (per Bank) VCCJ Power Supply Current All Devices All Devices All Devices All Devices Until DONE signal is active. For further information about supply current, please see the list of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. TJ = 25oC, power supplies at nominal voltage. A specific configuration pattern is used that scales with the size of the device; consists of 75% PFU utilization, 50% EBR, and 25% I/O configuration. 3-7 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet SERDES Power Supply Requirements (LatticeECP2M Family Only)1 Over Recommended Operating Conditions Symbol Standby (Power Down) ICCTX-SB ICCRX-SB ICCIB-SB ICCOB-SB ICCP-SB ICCAX33-SB ICCTX-OP ICCRX-OP ICCIB-OP ICCOB-OP ICCP-OP ICCAX33-OP VCCTX current (per channel) VCCRX current (per channel) Input buffer current (per channel) Output buffer current (per channel) SERDES PLL current (per quad) SERDES termination current (per quad) VCCTX current (per channel) VCCRX current (per channel) Input buffer current (per channel) Output buffer current (per channel) SERDES PLL current (per quad) SERDES termination current (per quad) 10 75 0 0 30 10 19 34 4 13 26 0.01 A A A A A A mA mA mA mA mA mA Description Typ.2 Units Operating (Data Rate = 3.125 Gbps) 1. Equalization enabled, pre-emphasis disabled. 2. TJ = 25C, power supplies at nominal voltage. SERDES Power (LatticeECP2M Family Only) Table 3-1 presents the SERDES power for one channel. Table 3-1. SERDES Power1 Symbol PS-1CH-31 PS-1CH-25 PS-1CH-12 PS-1CH-02 Description SERDES power (one channel @ 3.125 Gbps) SERDES power (one channel @ 2.5 Gbps) SERDES power (one channel @ 1.25 Gbps) SERDES power (one channel @ 250 Mbps) Typ.2 90 87 86 76 Units mW mW mW mW 1. One quarter of the total quad power (includes contribution from common circuits, all channels in the quad operating, pre-emphasis disabled, equalization enabled). 2. Typical values measured at 25oC and 1.2V. 3-8 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet sysI/O Recommended Operating Conditions VCCIO Standard LVCMOS 3.32 LVCMOS 2.52 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.22 LVTTL2 PCI SSTL18 Class I, II SSTL22 Class I, II SSTL3 Class I, II HSTL2 15 Class I HSTL 18 Class I, II LVDS2 MLVDS251 LVPECL331, 2 BLVDS25 RSDS1, 2 SSTL18D_I , II 2 2 2 1, 2 2 2 2 VREF (V) Max. 3.465 2.625 1.89 1.575 1.26 3.465 3.465 1.89 2.625 3.465 1.575 1.89 2.625 2.625 3.465 2.625 2.625 1.89 2.625 3.465 1.575 1.89 Min. -- -- -- -- -- -- -- 0.833 1.15 1.3 0.68 0.816 -- -- -- -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- 0.9 1.25 1.5 0.75 0.9 -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.969 1.35 1.7 0.9 1.08 -- -- -- -- -- -- -- -- -- -- Min. 3.135 2.375 1.71 1.425 1.14 3.135 3.135 1.71 2.375 3.135 1.425 1.71 2.375 2.375 3.135 2.375 2.375 1.71 2.375 3.135 1.425 2 Typ. 3.3 2.5 1.8 1.5 1.2 3.3 3.3 1.8 2.5 3.3 1.5 1.8 2.5 2.5 3.3 2.5 2.5 1.8 2.5 3.3 1.5 1.8 SSTL25D_ I2, II2 SSTL33D_ I , II HSTL15D_ I2 HSTL18D_ I , II 2 2 1.71 1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. Input on this standard does not depend on the value of VCCIO. 3-9 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet sysI/O Single-Ended DC Electrical Characteristics Input/Output Standard LVCMOS 3.3 VIL Min. (V) -0.3 Max. (V) 0.8 Min. (V) 2.0 VIH Max. (V) 3.6 VOL Max. (V) 0.4 0.2 LVTTL -0.3 0.8 2.0 3.6 0.4 0.2 LVCMOS 2.5 -0.3 0.7 1.7 3.6 0.4 0.2 LVCMOS 1.8 -0.3 0.35 VCCIO 0.65 VCCIO 3.6 0.4 0.2 LVCMOS 1.5 LVCMOS 1.2 PCI SSTL3 Class I SSTL3 Class II SSTL2 Class I SSTL2 Class II SSTL18 Class I SSTL18 Class II HSTL Class I HSTL18 Class I HSTL18 Class II -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.35 VCCIO 0.35 VCC 0.3 VCCIO VREF - 0.2 VREF - 0.2 VREF - 0.18 VREF - 0.18 0.65 VCCIO 0.65 VCC 0.5 VCCIO VREF + 0.2 VREF + 0.2 VREF + 0.18 VREF + 0.18 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.2 0.4 0.2 VOH Min. (V) VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 IOL1 (mA) 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 20, 16, 12, 8, 4 0.1 16, 12, 8, 4 0.1 8, 4 0.1 6, 2 0.1 1.5 8 16 7.6 12 15.2 20 6.7 8 11 4 8 8 12 16 IOH1 (mA) -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -20, -16, -12, -8, -4 -0.1 -16, -12, -8, -4 -0.1 -8, -4 -0.1 -6, -2 -0.1 -0.5 -8 -16 -7.6 -12 -15.2 -20 -6.7 -8 -11 -4 -8 -8 -12 -16 0.1 VCCIO 0.9 VCCIO 0.7 VCCIO - 1.1 0.5 0.54 0.35 0.4 0.28 0.4 0.4 0.4 VCCIO - 0.9 VCCIO - 0.62 VCCIO - 0.43 VCCIO - 0.4 VCCIO - 0.28 VCCIO - 0.4 VCCIO - 0.4 VCCIO - 0.4 VREF - 0.125 VREF + 0.125 VREF - 0.125 VREF + 0.125 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3-10 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet sysI/O Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Parameter VINP, VINM VCM VTHD IIN VOH VOL VOD VOD VOS VOS ISA ISAB Description Input Voltage Input Common Mode Voltage Differential Input Threshold Input Current Output High Voltage for VOP or VOM Output Low Voltage for VOP or VOM Output Voltage Differential Change in VOD Between High and Low Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current Output Short Circuit Current VOD = 0V Driver Outputs Shorted to Ground VOD = 0V Driver Outputs Shorted to Each Other (VOP + VOM)/2, RT = 100 Ohm Half the Sum of the Two Inputs Difference Between the Two Inputs Power On or Power Off RT = 100 Ohm RT = 100 Ohm (VOP - VOM), RT = 100 Ohm Test Conditions Min. 0 0.05 +/-100 -- -- 0.9V 250 -- 1.125 -- -- -- Typ. -- -- -- -- 1.38 1.03 350 -- 1.20 -- -- -- Max. 2.4 2.35 -- +/-10 1.60 -- 450 50 1.375 50 24 12 Units V V mV A V V mV mV V mV mA mA Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. For further information about LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see the list of additional technical information at the end of this data sheet. 3-11 Lattice Semiconductor LVDS25E DC and Switching Characteristics LatticeECP2/M Family Data Sheet The top and bottom sides of LatticeECP2/M devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example VCCIO = 2.5V (5%) RS=158 ohms (1%) 8 mA VCCIO = 2.5V (5%) RS=158 ohms (1%) 8 mA RP = 140 ohms (1%) RT = 100 ohms (1%) + - Transmission line, Zo = 100 ohm differential ON-chip OFF-chip OFF-chip ON-chip Table 3-2. LVDS25E DC Conditions Parameter VCCIO ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage Output Low Voltage Output Differential Voltage Output Common Mode Voltage Back Impedance DC Output Current Typical 2.50 20 158 140 100 1.43 1.07 0.35 1.25 100.5 6.03 Units V V V V V mA LVCMOS33D All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to 4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. 3-12 Lattice Semiconductor BLVDS DC and Switching Characteristics LatticeECP2/M Family Data Sheet The LatticeECP2/M devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5V 16mA RS = 90 ohms RS = 90 ohms 2.5V 16mA 45-90 ohms 2.5V 16mA RTL 45-90 ohms RTR 2.5V 16mA RS = 90 ohms RS = 90 ohms + - RS = 90 ohms ... + RS = 90 ohms RS = 90 ohms RS = 90 ohms + - 2.5V 16mA 2.5V 16mA 2.5V 16mA 2.5V 16mA - Table 3-3. BLVDS DC Conditions1 Over Recommended Operating Conditions Typical Parameter VCCIO ZOUT RS RTL RTR VOH VOL VOD VCM IDC Description Output Driver Supply (+/- 5%) Driver Impedance Driver Series Resistor (+/- 1%) Driver Parallel Resistor (+/- 1%) Receiver Termination (+/- 1%) Output High Voltage Output Low Voltage Output Differential Voltage Output Common Mode Voltage DC Output Current Zo = 45 2.50 10.00 90.00 45.00 45.00 1.38 1.12 0.25 1.25 11.24 Zo = 90 2.50 10.00 90.00 90.00 90.00 1.48 1.02 0.46 1.25 10.20 Units V V V V V mA 1. For input buffer, see LVDS table. 3-13 + Lattice Semiconductor LVPECL DC and Switching Characteristics LatticeECP2/M Family Data Sheet The LatticeECP2/M devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals. Figure 3-3. Differential LVPECL VCCIO = 3.3V (+/-5%) 16mA VCCIO = 3.3V (+/-5%) 16mA On-chip Off-chip + - RS = 93.1 ohms (+/-1%) RS = 93.1 ohms (+/-1%) RP = 196 ohms (+/-1%) RT = 100 ohms (+/-1%) Transmission line, Zo = 100 ohm differential Off-chip On-chip Table 3-4. LVPECL DC Conditions1 Over Recommended Operating Conditions Parameter VCCIO ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage Output Low Voltage Output Differential Voltage Output Common Mode Voltage Back Impedance DC Output Current Typical 3.30 10 93 196 100 2.05 1.25 0.80 1.65 100.5 12.11 Units V V V V V mA 1. For input buffer, see LVDS table. 3-14 Lattice Semiconductor RSDS DC and Switching Characteristics LatticeECP2/M Family Data Sheet The LatticeECP2/M devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. Figure 3-4. RSDS (Reduced Swing Differential Signaling) VCCIO = 2.5V (+/-5%) 8mA VCCIO = 2.5V (+/-5%) 8mA On-chip Off-chip RP = 121 ohms (+/-1%) RT = 100 ohms (+/-1%) + RS = 294 ohms (+/-1%) RS = 294 ohms (+/-1%) Transmission line, Zo = 100 ohm differential Off-chip On-chip Table 3-5. RSDS DC Conditions1 Over Recommended Operating Conditions Parameter VCCIO ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage Output Low Voltage Output Differential Voltage Output Common Mode Voltage Back Impedance DC Output Current Typical 2.50 20 294 121 100 1.35 1.15 0.20 1.25 101.5 3.66 Units V V V V V mA 1. For input buffer, see LVDS table. 3-15 Lattice Semiconductor MLVDS DC and Switching Characteristics LatticeECP2/M Family Data Sheet The LatticeECP2/M devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors. Figure 3-5. MLVDS (Multipoint Low Voltage Differential Signaling) Heavily loaded backplace, effective Zo~50 to 70 ohms differential 2.5V 16mA RTL 50 to 70 ohms +/-1% 50 to 70 ohms +/-1% RTR RS = 35ohms RS = 35ohms 2.5V 16mA 2.5V 16mA 2.5V 16mA RS = 35ohms + RS = 35ohms RS = 35ohms RS = 35ohms RS = 35ohms RS = 35ohms + - ... + + 2.5V 16mA 16mA 2.5V 16mA 2.5V 16mA 2.5V Table 3-6. MLVDS DC Conditions1 Typical Parameter VCCIO ZOUT RS RTL RTR VOH VOL VOD VCM IDC Description Output Driver Supply (+/-5%) Driver Impedance Driver Series Resistor (+/-1%) Driver Parallel Resistor (+/-1%) Receiver Termination (+/-1%) Output High Voltage Output Low Voltage Output Differential Voltage Output Common Mode Voltage DC Output Current Zo=50 2.50 10.00 35.00 50.00 50.00 1.52 0.98 0.54 1.25 21.74 Zo=70 2.50 10.00 35.00 70.00 70.00 1.60 0.90 0.70 1.25 20.00 Units V V V V V mA 1. For input buffer, see LVDS table. For further information about LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see the list of additional technical information at the end of this data sheet. - 3-16 - Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet Typical Building Block Function Performance1 Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 3.8 4.5 5.0 3.2 3.4 3.5 4.0 ns ns ns ns ns ns ns -7 Timing Units 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Timing v.A 0.11 Register-to-Register Performance Function Basic Functions 16-bit Decoder 32-bit Decoder 64-bit Decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX 8-bit Adder 16-bit Adder 64-bit Adder 16-bit Counter 32-bit Counter 64-bit Counter 64-bit Accumulator Embedded Memory Functions 512x36 Single Port RAM, EBR Output Registers 1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers) 1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers) Distributed Memory Functions 16x4 Pseudo-Dual Port RAM (One PFU) 32x4 Pseudo-Dual Port RAM 64x8 Pseudo-Dual Port RAM DSP Functions 18x18 Multiplier (All Registers) 420 MHz 819 521 435 MHz MHz MHz 370 370 MHz MHz 599 542 417 847 803 660 577 591 500 306 488 378 260 253 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz -7 Timing Units 280 MHz 3-17 Lattice Semiconductor Register-to-Register Performance (Continued) Function 9x9 Multiplier (All Registers) 36x36 Multiplier (All Registers) 18x18 Multiplier/Accumulate (Input and Output Registers) 18x18 Multiplier-Add/Sub-Sum (All Registers) DSP IP Functions 16-Tap Fully-Parallel FIR Filter 1024-pt, Radix 4, Decimation in Frequency FFT 8x8 Matrix Multiplier Timing v.A 0.11 DC and Switching Characteristics LatticeECP2/M Family Data Sheet -7 Timing 420 372 295 420 Units MHz MHz MHz MHz 304 227 223 MHz MHz MHz Derating Timing Tables Logic timing provided in the following sections of this data sheet and the ispLEVER design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage. 3-18 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M External Switching Characteristics9 Over Recommended Operating Conditions -7 Parameter Description Device LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tCO Clock to Output - PIO Output Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tSU Clock to Data Setup - PIO Input Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tH Clock to Data Hold - PIO Input Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 Min. -- -- -- -- -- -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.80 1.80 1.80 Max. 3.50 3.50 3.50 3.50 3.50 3.70 3.90 3.90 4.50 4.50 4.50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. -- -- -- -- -- -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 2.10 2.10 2.10 General I/O Pin Parameters (using Primary Clock without PLL)1 3.90 3.90 3.90 3.90 3.90 4.10 4.30 4.30 5.00 5.00 5.00 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 2.30 2.30 2.30 4.20 4.20 4.20 4.20 4.20 4.40 4.70 4.70 5.40 5.40 5.40 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -6 Max. Min. -5 Max. Units 3-19 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M External Switching Characteristics9 (Continued) Over Recommended Operating Conditions -7 Parameter Description Device LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tSU_DEL Clock to Data Setup - PIO Input Register with Data Input Delay LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tH_DEL Clock to Data Hold - PIO Input RegLFE2-70 ister with Input Data Delay LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 fMAX_IO Clock Frequency of I/O Register and ECP2/M PFU Register LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tCOE Clock to Output - PIO Output Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 Min. 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 420 Min. 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- -6 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 357 Min. 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 1.90 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- -5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 311 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz General I/O Pin Parameters (using Edge Clock without PLL)1 -- -- -- -- -- -- -- -- -- -- -- 2.60 2.60 2.60 2.60 2.60 2.60 2.60 2.60 3.10 3.10 3.10 -- -- -- -- -- -- -- -- -- -- -- 2.90 2.90 2.90 2.90 2.90 2.90 2.90 2.90 3.40 3.40 3.40 -- -- -- -- -- -- -- -- -- -- -- 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.20 3.70 3.70 3.70 ns ns ns ns ns ns ns ns ns ns ns 3-20 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M External Switching Characteristics9 (Continued) Over Recommended Operating Conditions -7 Parameter Description Device LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tSUE Clock to Data Setup - PIO Input Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tHE Clock to Data Hold - PIO Input Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tSU_DELE Clock to Data Setup - PIO Input Register with Data Input Delay LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 Min. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90 1.20 1.20 1.20 1.00 1.00 1.00 1.00 1.00 1.00 1.20 1.20 1.20 1.20 1.20 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.40 1.40 1.40 1.30 1.30 1.30 1.30 1.30 1.30 1.60 1.60 1.60 1.60 1.60 -6 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.90 1.90 1.90 1.90 1.90 -5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-21 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M External Switching Characteristics9 (Continued) Over Recommended Operating Conditions -7 Parameter Description Device LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tH_DELE Clock to Data Hold - PIO Input Register with Input Data Delay LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 fMAX_IOE Clock Frequency of I/O and PFU Register ECP2/M Min. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- Max. -- -- -- -- -- -- -- -- -- -- -- 420 Min. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- -6 Max. -- -- -- -- -- -- -- -- -- -- -- 357 Min. 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- -5 Max. -- -- -- -- -- -- -- -- -- -- -- 311 Units ns ns ns ns ns ns ns ns ns ns ns MHz General I/O Pin Parameters (using Primary Clock with PLL)1 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tCOPLL10 Clock to Output - PIO Output Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tSUPLL Clock to Data Setup - PIO Input Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 -- -- -- -- -- -- -- -- -- -- -- 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.70 0.80 2.30 2.30 2.30 2.30 2.30 2.30 2.30 2.30 2.60 2.60 2.70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.80 0.90 2.60 2.60 2.60 2.60 2.60 2.60 2.60 2.60 2.90 2.90 3.00 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90 0.90 1.00 2.80 2.80 2.80 2.80 2.80 2.80 2.80 2.80 3.10 3.10 3.20 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-22 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M External Switching Characteristics9 (Continued) Over Recommended Operating Conditions -7 Parameter Description Device LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tHPLL Clock to Data Hold - PIO Input Register LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tSU_DELPLL Clock to Data Setup - PIO Input Register with Data Input Delay LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 LFE2-6 LFE2-12 LFE2-20 LFE2-35 LFE2-50 tH_DELPLL Clock to Data Hold - PIO Input Register with Input Data Delay LFE2-70 LFE2M20 LFE2M35 LFE2M50 LFE2M70 LFE2M100 DDR I/O Pin Parameters2 tDVADQ tDVEDQ tDQVBS tDQVAS fMAX_DDR tDVADQ tDVEDQ Data Valid After DQS (DDR Read) Data Hold After DQS (DDR Read) Data Valid After DQS (DDR Write) DDR Clock Frequency 6 -6 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.225 -- -- -- 200 0.225 -- Min. 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 1.20 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.00 2.10 2.10 2.20 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.640 0.250 0.250 95 -- 0.640 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.225 -- -- -- 166 0.225 -- Min. 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 1.40 2.20 2.20 2.20 2.20 2.20 2.20 2.20 2.20 2.30 2.30 2.40 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.640 0.250 0.250 95 -- 0.640 -5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.225 -- -- -- 133 0.225 -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UI UI UI UI MHz UI UI Min. 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.90 1.90 2.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.640 0.250 0.250 95 -- 0.640 ECP2/M ECP2/M ECP2/M ECP2/M ECP2/M ECP2/M Data Valid Before DQS (DDR Write) ECP2/M DDR2 I/O Pin Parameters3 Data Valid After DQS (DDR Read) Data Hold After DQS (DDR Read) 3-23 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M External Switching Characteristics9 (Continued) Over Recommended Operating Conditions -7 Parameter tDQVBS tDQVAS fMAX_DDR2 Description Data Valid After DQS (DDR Write) DDR Clock Frequency Device ECP2/M ECP2/M ECP2-20 ECP2-35 ECP2-50 ECP2-70 Maximum Data Rate ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 ECP2-20 ECP2-35 ECP2-50 ECP2-70 tDVACLKSPI Data Valid After CLK (Receive) ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 ECP2-20 ECP2-35 ECP2-50 ECP2-70 tDVECLKSPI Data Hold After CLK (Receive) ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 ECP2-20 ECP2-35 ECP2-50 ECP2-70 tDIASPI Data Invalid After Clock (Transmit) ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 Min. 0.250 0.250 133 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.75 0.75 0.75 0.75 0.79 0.79 0.79 0.79 0.79 -- -- -- -- -- -- -- -- -- Max. -- -- 266 750 750 750 750 622 622 622 622 622 0.25 0.25 0.25 0.25 0.21 0.21 0.21 0.21 0.21 -- -- -- -- -- -- -- -- -- 280 280 280 280 230 230 230 230 230 Min. 0.250 0.250 133 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.75 0.75 0.75 0.75 0.79 0.79 0.79 0.79 0.79 -- -- -- -- -- -- -- -- -- Data Valid Before DQS (DDR Write) ECP2/M -6 Max. -- -- 200 622 622 622 622 622 622 622 622 622 0.25 0.25 0.25 0.25 0.21 0.21 0.21 0.21 0.21 -- -- -- -- -- -- -- -- -- 280 280 280 280 230 230 230 230 230 Min. 0.250 0.250 133 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.75 0.75 0.75 0.75 0.79 0.79 0.79 0.79 0.79 -- -- -- -- -- -- -- -- -- -5 Max. -- -- 166 622 622 622 622 622 622 622 622 622 0.25 0.25 0.25 0.25 0.21 0.21 0.21 0.21 0.21 -- -- -- -- -- -- -- -- -- 280 280 280 280 230 230 230 230 230 Units UI UI MHz Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps Mbps UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI ps ps ps ps ps ps ps ps ps SPI4.2 I/O Pin Parameters Static Alignment4, 8, 11 3-24 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M External Switching Characteristics9 (Continued) Over Recommended Operating Conditions -7 Parameter Description Device ECP2-20 ECP2-35 ECP2-50 ECP2-70 tDIBSPI Data Invalid Before Clock (Transmit) ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 XGMII I/O Pin Parameters (312 Mbps)5 tSUXGMII tHXGMII Data Setup Before Read Clock Data Hold After Read Clock ECP2/M ECP2/M ECP2/M ECP2/M ECP2/M ECP2/M ECP2/M ECP2/M 480 480 960 960 -- 0.95 -- -- 0.95 -- -- -- -- -- 420 -- 300 420 -- 300 480 480 960 960 -- 1.19 -- -- 1.19 -- -- -- -- -- 357 -- 360 357 -- 360 480 480 960 960 -- 2.00 -- -- 2.00 -- -- -- -- -- 311 -- 420 311 -- 420 ps ps ps ps MHz ns ps MHz ns ps Min. -- -- -- -- -- -- -- -- -- Max. 280 280 280 280 230 230 230 230 230 Min. -- -- -- -- -- -- -- -- -- -6 Max. 280 280 280 280 230 230 230 230 230 Min. -- -- -- -- -- -- -- -- -- -5 Max. 280 280 280 280 230 230 230 230 230 Units ps ps ps ps ps ps ps ps ps tDVBCKXGMII Data Valid Before Clock tDVACKXGMII Data Valid After Clock Primary fMAX_PRI7 tW_PRI tSKEW_PRI Edge Clock fMAX_EDGE7 Frequency for Edge Clock tW_EDGE Clock Pulse Width for Edge Clock Frequency for Primary Clock Tree Primary Clock Skew Within a Bank Clock Pulse Width for Primary Clock ECP2/M Edge Clock Skew Within an Edge of ECP2/M tSKEW_EDGE the Device 1. 2. 3. 4. 5. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load. DDR timing numbers based on SSTL25 for BGA packages only. DDR2 timing numbers based on SSTL18 for BGA packages only. SPI4.2 and SFI4 timing numbers based on LVDS25 for BGA packages only. XGMII timing numbers based on HSTL class I. A corresponding left/right dedicated clock buffer is used when using the SPI4.2 interface to the left or right edge of the device. For SPI4.2 mode, the software tool will help in selecting the appropriate clock buffer. 6. IP will be used to support DDR and DDR2 memory data rates down to 95MHz. This approach uses a free-running clock and PFU register to sample the data instead of the hardwired DDR memory interface. 7. Using the LVDS I/O standard. 8. ECP2-6 and ECP2-12 do not support SPI4.2 9. The AC numbers do not apply to PCLK6 and PCLK7. 10. Applies to CLKOP only. 11. Please refer to technical note TN1159, LatticeECP2M Pin Assignment Recommendations for best performance. Timing v.A 0.11 3-25 Lattice Semiconductor Figure 3-6. SPI4.2 Parameters tDIBSPI CLK DC and Switching Characteristics LatticeECP2/M Family Data Sheet Transmit Parameters tDIASPI Data (TDAT, TCTL) tDIASPI tDIBSPI Receiver Parameters RDTCLK Data (RDAT,RCTL) tDVACLKSPI tDVECLKSPI tDVACLKSPI tDVECLKSPI 3-26 Lattice Semiconductor Figure 3-7. DDR and DDR2 Parameters DC and Switching Characteristics LatticeECP2/M Family Data Sheet Transmit Parameters DQS DQ tDQVBS tDQVAS tDQVBS tDQVAS Receiver Parameters DQS DQ tDVADQ tDVEDQ Figure 3-8. XGMII Parameters tDVADQ tDVEDQ Transmit Parameters CLOCK DATA tDVBCKXGMII t DVACKXGMII t DVBCKXGMII t DVACKXGMII Receiver Parameters CLOCK DATA tSUXGMII tHXGMII tSUXGMII tHXGMII 3-27 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M Internal Switching Characteristics1 Over Recommended Operating Conditions -7 Parameter PFU/PFF Logic Mode Timing tLUT4_PFU tLUT6_PFU tLSR_PFU tSUM_PFU tHM_PFU tSUD_PFU tHD_PFU tCK2Q_PFU LUT4 delay (A to D inputs to F output) LUT6 delay (A to D inputs to OFX output) Set/Reset to output of PFU (Asynchronous) Clock to Mux (M0,M1) Input Setup Time Clock to Mux (M0,M1) Input Hold Time Clock to D input setup time Clock to D input hold time Clock to Q delay, (D-type Register Configuration) Clock to Output (F Port) Data Setup Time Data Hold Time Address Setup Time Address Hold Time Write/Read Enable Setup Time Write/Read Enable Hold Time -- -- -- 0.128 -0.051 0.061 0.002 -- 0.180 0.304 0.600 -- -- -- -- 0.285 -- -- -- 0.129 -0.049 0.071 0.003 -- 0.198 0.331 0.655 -- -- -- -- 0.309 -- -- -- 0.129 -0.046 0.081 0.003 -- 0.216 0.358 0.711 -- -- -- -- 0.333 ns ns ns ns ns ns ns ns Description Min. Max. Min. -6 Max. Min. -5 Max. Units PFU Dual Port Memory Mode Timing tCORAM_PFU tSUDATA_PFU tHDATA_PFU tSUADDR_PFU tHADDR_PFU tSUWREN_PFU tHWREN_PFU PIC Timing PIO Input/Output Buffer Timing tIN_PIO tOUT_PIO Input Buffer Delay (LVCMOS25) Output Buffer Delay (LVCMOS25) Input Register Setup Time (Data Before Clock) Input Register Hold Time (Data after Clock) Output Register Clock to Output Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Set/Reset Setup Time Set/Reset Hold Time Clock (Read) to output from Address or Data Clock (Write) to output from EBR output Register Setup Data to EBR Memory Hold Data to EBR Memory Setup Address to EBR Memory Hold Address to EBR Memory Setup Write/Read Enable to PFU Memory -- -- 0.613 1.115 -- -- 0.681 1.115 -- -- 0.749 1.343 ns ns -- -0.172 0.199 -0.245 0.246 -0.122 0.132 0.902 -- -- -- -- -- -- -- -0.205 0.235 -0.284 0.285 -0.145 0.156 1.083 -- -- -- -- -- -- -- -0.238 0.271 -0.323 0.324 -0.168 0.180 1.263 -- -- -- -- -- -- ns ns ns ns ns ns ns IOLOGIC Input/Output Timing tSUI_PIO tHI_PIO tCOO_PIO tSUCE_PIO tHCE_PIO tSULSR_PIO tHLSR_PIO EBR Timing tCO_EBR tCOO_EBR tSUDATA_EBR tHDATA_EBR tSUADDR_EBR tHADDR_EBR tSUWREN_EBR -- -- -0.157 0.173 -0.115 0.138 -0.128 2.51 0.33 -- -- -- -- -- -- -- -0.181 0.195 -0.130 0.155 -0.149 2.75 0.36 -- -- -- -- -- -- -- -0.205 0.217 -0.145 0.172 -0.170 2.99 0.39 -- -- -- -- -- ns ns ns ns ns ns ns 0.596 -0.570 -- 0.032 -0.022 0.184 -0.080 -- -- 0.61 -- -- -- -- 0.645 -0.614 -- 0.037 -0.025 0.201 -0.086 -- -- 0.66 -- -- -- -- 0.694 -0.658 -- 0.041 -0.028 0.217 -0.093 -- -- 0.72 -- -- -- -- ns ns ns ns ns ns ns 3-28 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M Internal Switching Characteristics1 (Continued) Over Recommended Operating Conditions -7 Parameter tHWREN_EBR tSUCE_EBR tHCE_EBR tRSTO_EBR tSUBE_EBR tHBE_EBR GPLL Parameters tRSTREC_GPLL SPLL Parameters tRSTREC_SPLL tSUI_DSP tHI_DSP tSUP_DSP ttHP_DSP tSUO_DSP tHO_DSP tCOI_DSP tCOP_DSP tCOO_DSP tSUADDSUB tHADDSUB Reset Recovery to Rising Clock Input Register Setup Time Input Register Hold Time Pipeline Register Setup Time Pipeline Register Hold Time Output Register Setup Time Output Register Hold Time Input Register Clock to Output Time Pipeline Register Clock to Output Time Output Register Clock to Output Time AddSub Input Register Setup Time AddSub Input Register Hold Time 1.00 0.12 0.02 2.18 -0.68 4.26 -1.25 -- -- -- -0.24 0.27 -- -- -- -- -- -- -- 3.92 1.87 0.50 -- -- 1.00 0.13 -0.01 2.42 -0.77 4.71 -1.40 -- -- -- -0.26 0.29 -- -- -- -- -- -- -- 4.30 1.98 0.52 -- -- 1.00 0.14 -0.03 2.66 -0.86 5.16 -1.54 -- -- -- -0.28 0.32 -- -- -- -- -- -- -- 4.68 2.08 0.55 -- -- ns ns ns ns ns ns ns ns ns ns ns ns DSP Block Timing2,3 Reset Recovery to Rising Clock 1.00 -- 1.00 -- 1.00 -- ns Description Hold Write/Read Enable to PFU Memory Clock Enable Setup Time to EBR Output Register Clock Enable Hold Time to EBR Output Register Reset To Output Delay Time from EBR Output Register Byte Enable Set-Up Time to EBR Output Register Byte Enable Hold Time to EBR Output Register Min. 0.139 0.123 -0.081 -- -0.115 0.138 Max. -- -- -- 1.03 -- -- Min. 0.156 0.134 -0.090 -- -0.130 0.155 -6 Max. -- -- -- 1.15 -- -- Min. 0.173 0.145 -0.100 -- -0.145 0.172 -5 Max. -- -- -- 1.26 -- -- Units ns ns ns ns ns ns 1. Internal parameters are characterized but not tested on every device. 2. These parameters apply to LatticeECP devices only. 3. DSP Block is configured in Multiply Add/Sub 18x18 Mode. Timing v.A 0.11 3-29 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet Timing Diagrams Figure 3-9. Read/Write Mode (Normal) CLKA CSA WEA ADA A0 tSU tH A1 A0 A1 A0 DIA D0 D1 tCO_EBR tCO_EBR D0 D1 tCO_EBR D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-10. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA A0 A1 A0 A1 A0 tSU tH DIA D0 D1 tCOO_EBR tCOO_EBR DOA (Regs) Mem(n) data from previous read output is only updated during a read cycle D0 D1 3-30 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet Figure 3-11. Write Through (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA Three consecutive writes to A0 ADA A0 tSU tH A1 A0 DIA D0 tACCESS D1 tACCESS D2 tACCESS D3 D4 tACCESS DOA Data from Prev Read or Write D0 D1 D2 D3 D4 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. 3-31 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M Family Timing Adders1, 2, 3 Over Recommended Operating Conditions Buffer Type Input Adjusters LVDS25 BLVDS25 MLVDS RSDS LVPECL33 HSTL18_I HSTL18_II HSTL18D_I HSTL18D_II HSTL15_I HSTL15D_I SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18_II SSTL18D_I SSTL18D_II LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33 Output Adjusters LVDS25E LVDS25 BLVDS25 MLVDS RSDS LVPECL33 HSTL18_I HSTL18_II HSTL18D_I HSTL18D_II LVDS 2.5 E4 LVDS 2.5 BLVDS 2.5 MLVDS 2.54 RSDS 2.54 LVPECL 3.34 HSTL_18 class I 8mA drive HSTL_18 class II Differential HSTL 18 class I 8mA drive Differential HSTL 18 class II 0.25 0.10 0.00 0.00 0.25 -0.02 -0.19 -0.30 -0.19 -0.30 0.19 0.13 -0.01 -0.01 0.19 -0.04 -0.22 -0.34 -0.22 -0.34 0.13 0.17 -0.03 -0.03 0.13 -0.06 -0.25 -0.37 -0.25 -0.37 ns ns ns ns ns ns ns ns ns ns LVDS BLVDS LVDS RSDS LVPECL HSTL_18 class I HSTL_18 class II Differential HSTL 18 class I Differential HSTL 18 class II HSTL_15 class I Differential HSTL 15 class I SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I SSTL_2 class II Differential SSTL_2 class I Differential SSTL_2 class II SSTL_18 class I SSTL_18 class II Differential SSTL_18 class I Differential SSTL_18 class II LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 PCI -0.04 -0.04 -0.15 -0.15 0.16 0.01 0.01 0.01 0.01 0.01 0.01 -0.03 -0.03 -0.03 -0.03 -0.04 -0.04 -0.04 -0.04 -0.01 -0.01 -0.01 -0.01 -0.16 -0.08 0.00 -0.16 -0.14 -0.04 -0.08 -0.02 -0.09 -0.15 -0.15 0.15 -0.01 -0.01 -0.01 -0.01 -0.01 -0.01 -0.07 -0.07 -0.07 -0.07 -0.07 -0.07 -0.07 -0.07 -0.04 -0.04 -0.04 -0.04 -0.16 -0.12 0.00 -0.17 -0.14 -0.01 -0.12 0.00 -0.15 -0.15 -0.15 0.13 -0.04 -0.04 -0.04 -0.04 -0.04 -0.04 -0.10 -0.10 -0.10 -0.10 -0.10 -0.10 -0.10 -0.10 -0.07 -0.07 -0.07 -0.07 -0.16 -0.16 0.00 -0.17 -0.14 0.01 -0.16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -7 -6 -5 Units 3-32 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type HSTL15_I HSTL15D_I SSTL33_I SSTL33_II SSTL33D_I SSTL33D_II SSTL25_I SSTL25_II SSTL25D_I SSTL25D_II SSTL18_I SSTL18_II SSTL18D_I SSTL18D_II LVTTL33_4mA LVTTL33_8mA LVTTL33_12mA LVTTL33_16mA LVTTL33_20mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_16mA LVCMOS33_20mA LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_16mA LVCMOS25_20mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_16mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_16mA LVCMOS33_20mA Description HSTL_15 class I 4mA drive Differential HSTL 15 class I 4mA drive SSTL_3 class I SSTL_3 class II Differential SSTL_3 class I Differential SSTL_3 class II SSTL_2 class I 8mA drive SSTL_2 class II 16mA drive Differential SSTL_2 class I 8mA drive Differential SSTL_2 class II 16mA drive SSTL_1.8 class I SSTL_1.8 class II 8mA drive Differential SSTL_1.8 class I Differential SSTL_1.8 class II 8mA drive LVTTL 4mA drive LVTTL 8mA drive LVTTL 12mA drive LVTTL 16mA drive LVTTL 20mA drive LVCMOS 3.3 4mA drive, fast slew rate LVCMOS 3.3 8mA drive, fast slew rate LVCMOS 3.3 12mA drive, fast slew rate LVCMOS 3.3 16mA drive, fast slew rate LVCMOS 3.3 20mA drive, fast slew rate LVCMOS 2.5 4mA drive, fast slew rate LVCMOS 2.5 8mA drive, fast slew rate LVCMOS 2.5 12mA drive, fast slew rate LVCMOS 2.5 16mA drive, fast slew rate LVCMOS 2.5 20mA drive, fast slew rate LVCMOS 1.8 4mA drive, fast slew rate LVCMOS 1.8 8mA drive, fast slew rate LVCMOS 1.8 12mA drive, fast slew rate LVCMOS 1.8 16mA drive, fast slew rate LVCMOS 1.5 4mA drive, fast slew rate LVCMOS 1.5 8mA drive, fast slew rate LVCMOS 1.2 2mA drive, fast slew rate LVCMOS 1.2 6mA drive, fast slew rate LVCMOS 3.3 4mA drive, slow slew rate LVCMOS 3.3 8mA drive, slow slew rate LVCMOS 3.3 12mA drive, slow slew rate LVCMOS 3.3 16mA drive, slow slew rate LVCMOS 3.3 20mA drive, slow slew rate -7 -0.22 -0.22 -0.12 -0.20 -0.12 -0.20 -0.16 -0.19 -0.16 -0.19 -0.14 -0.20 -0.14 -0.20 0.52 0.06 0.04 0.03 -0.09 0.52 0.06 0.04 0.03 -0.09 0.41 0.01 0.00 0.04 -0.09 0.37 0.10 -0.02 -0.02 0.29 0.05 0.58 0.13 2.17 2.50 1.72 1.64 1.33 -6 -0.25 -0.25 -0.15 -0.23 -0.15 -0.23 -0.19 -0.22 -0.19 -0.22 -0.17 -0.23 -0.17 -0.23 0.60 0.08 0.04 0.02 -0.09 0.60 0.08 0.04 0.02 -0.09 0.47 0.01 0.00 0.04 -0.10 0.40 0.12 -0.02 -0.03 0.31 0.05 0.69 0.19 2.44 2.67 1.88 1.63 1.36 -5 -0.27 -0.27 -0.18 -0.27 -0.18 -0.27 -0.22 -0.25 -0.22 -0.25 -0.20 -0.25 -0.20 -0.25 0.68 0.09 0.05 0.02 -0.10 0.68 0.09 0.05 0.02 -0.10 0.53 0.00 0.00 0.04 -0.11 0.43 0.13 -0.02 -0.03 0.32 0.06 0.79 0.26 2.71 2.83 2.05 1.62 1.39 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3-33 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_16mA LVCMOS25_20mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_16mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA PCI33 Description LVCMOS 2.5 4mA drive, slow slew rate LVCMOS 2.5 8mA drive, slow slew rate LVCMOS 2.5 12mA drive, slow slew rate LVCMOS 2.5 16mA drive, slow slew rate LVCMOS 2.5 20mA drive, slow slew rate LVCMOS 1.8 4mA drive, slow slew rate LVCMOS 1.8 8mA drive, slow slew rate LVCMOS 1.8 12mA drive, slow slew rate LVCMOS 1.8 16mA drive, slow slew rate LVCMOS 1.5 4mA drive, slow slew rate LVCMOS 1.5 8mA drive, slow slew rate LVCMOS 1.2 2mA drive, slow slew rate LVCMOS 1.2 6mA drive, slow slew rate PCI33 -7 2.18 2.19 1.50 1.60 1.43 2.22 1.93 1.43 1.47 2.32 1.84 2.52 1.69 0.04 -6 2.26 2.35 1.66 1.59 1.39 2.27 2.08 1.51 1.46 2.38 1.98 2.63 1.83 0.04 -5 2.33 2.51 1.82 1.58 1.34 2.32 2.23 1.58 1.45 2.43 2.12 2.74 1.96 0.04 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. Timing Adders are characterized but not tested on every device. 2. LVCMOS timing measured with the load specified in Switching Test Condition table. 3. All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing v.A 0.11 3-34 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet sysCLOCK GPLL Timing Over Recommended Operating Conditions Parameter fIN fOUT fOUT2 fVCO fPFD Description Input Clock Frequency (CLKI, CLKFB) Output Clock Frequency (CLKOP, CLKOS) K-Divider Output Frequency (CLKOK) PLL VCO Frequency Phase Detector Input Frequency Without external capacitor With external capacitor 5, 6 Conditions Without external capacitor With external capacitor 5, 6 Min. 20 2 20 5 0.156 0.039 640 20 2 45 -- -- -- -- -- 1 -- -- 85 -- -- Typ. -- -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- -- 130 -- -- -- -- -- -- -- Max. 420 420 420 50 210 25 1280 420 50 55 0.05 125 0.025 0.04 250 -- 150 500 360 200 10 -- -- -- -- -- Units MHz MHz MHz MHz MHz MHz MHz MHz MHz % UI ps UIPP UIPP ps ns s s ps ps ns ns ns ns ns s Without external capacitor With external capacitor5 Without external capacitor With external capacitor 5 AC Characteristics tDT tPH 4 Output Clock Duty Cycle Output Phase Accuracy Default duty cycle selected3 fOUT 100 MHz tOPJIT tSK tW 1 Output Clock Period Jitter Input Clock to Output Clock Skew Output Clock Pulse Width PLL Lock-in Time Programmable Delay Unit Input Clock Period Jitter External Feedback Delay Input Clock High Time Input Clock Low Time RST Pulse Width (RESETM/RESETK) 50 fOUT < 100 MHz fOUT < 50 MHz N/M = integer At 90% or 10% Without external capacitor With external capacitor5 tLOCK2 tPA tIPJIT tFBKDLY tHI tLO tRST 90% to 90% 10% to 10% Without external capacitor With external capacitor5 0.5 0.5 15 500 20 Reset Signal Pulse Width (CNTRST) 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Relative to CLKOP. 5. Value of external capacitor: 5.6 nF 20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin. 6. fOUT (max) = fIN * 10 for fIN < 5MHz. Timing v.A 0.11 3-35 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet sysCLOCK SPLL Timing Over Recommended Operating Conditions Parameter fIN fOUT fOUT2 fVCO fPFD Description Input Clock Frequency (CLKI, CLKFB) Output Clock Frequency (CLKOP, CLKOS) K-Divider Output Frequency (CLKOK) PLL VCO Frequency Phase Detector Input Frequency Without external capacitor With external capacitor 6 Conditions Without external capacitor With external capacitor With external capacitor With external capacitor 5, 6 Min. 33 2 33 5 0.258 0.039 640 33 2 45 -- -- -- -- -- 1 -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 420 420 420 50 210 25 1280 420 50 55 0.05 125 0.025 0.04 250 -- 150 500 200 10 -- -- -- -- -- Units MHz MHz MHz MHz MHz MHz MHz MHz MHz % UI ps UIPP UIPP ps ns s s ps ns ns ns ns ns s Without external capacitor 5 Without external capacitor 5 AC Characteristics tDT tPH 4 Output Clock Duty Cycle Output Phase Accuracy Default Duty Cycle Selected3 fOUT 100 MHz tOPJIT tSK tW 1 Output Clock Period Jitter Input Clock to Output Clock Skew Output Clock Pulse Width PLL Lock-in Time Input Clock Period Jitter External Feedback Delay Input Clock High Time Input Clock Low Time RST Pulse Width (RESETM/RESETK) 50 fOUT < 100 MHz fOUT < 50 MHz Divider Ratio = Integer At 90% or 10% Without external capacitor With external capacitor5 tLOCK2 tIPJIT tFBKDLY tHI tLO tRST 90% to 90% 10% to 10% Without external capacitor With external capacitor 5 0.5 0.5 15 500 20 Reset Signal Pulse Width (CNTRST) 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Phase accuracy of CLKOS compared to CLKOP. 5. Value of external capacitor: 5.6 nF 20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin. 6. fOUT (max) = fIN * 10 for fIN < 5MHz. Timing v.A 0.11 3-36 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet DLL Timing Over Recommended Operating Conditions Parameter fREF fFB fCLKOP1 fCLKOS2 tPJIT tCYJIT tDUTY tDUTYTRD tDUTYCIR tSKEW3 tPWH tPWL tR, tF tINSTB tLOCK tRSWD tPA tRANGE1 tRANGE4 Description Input reference clock frequency (on-chip or off-chip) Feedback clock frequency (on-chip or off-chip) Output clock frequency, CLKOP Output clock frequency, CLKOS Output clock period jitter (clean input) Output clock cycle to cycle jitter (clean input) Output clock duty cycle (at 50% levels, 50% duty cycle input clock, 50% duty cycle circuit turned off, time reference delay mode) Output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit enabled, time reference delay mode) Output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit enabled, clock injection removal mode) Output clock to clock skew between two outputs with the same phase setting Input clock minimum pulse width high (at 80% level) Input clock minimum pulse width low (at 20% level) Input clock rise and fall time (20% to 80% levels) Input clock period jitter DLL lock time Digital reset minimum pulse width (at 80% level) Delay step size Max. delay setting for single delay block (144 taps) Max. delay setting for four chained delay blocks 35 40 40 -- 750 750 -- -- 18,500 3 16.5 2.376 9.504 -- -- -- -- -- -- -- 42 6 24 Min. 100 100 100 25 Typ. -- -- -- -- -- Max. 500 500 500 500 250 250 65 60 60 100 -- -- 1 +/-250 -- -- 59.4 8.553 34.214 Units MHz MHz MHz MHz ps p-p ps p-p % % % ps ps ps ns ps cycles ns ps ns ns 1. CLKOP runs at the same frequency as the input clock. 2. CLKOS minimum frequency is obtained with divide by 4. 3. This is intended to be a "path-matching" design guideline and is not a measurable specification. Timing v.A 0.11 3-37 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet SERDES High Speed Data Transmitter (LatticeECP2M Family Only)1, 2 Table 3-7. Serial Output Timing and Levels Symbol VTX-DIFF-P-P-1.4 VTX-DIFF-P-P-1.0 VTX-DIFF-P-P-1.2 VOCM TTX-R TTX-F ZTX-OI-SE RLTX-RL Description Differential swing (1.4V setting)1, 2 Differential swing (1.0V setting)1, 2 Differential swing (1.2V setting) Output common mode voltage Rise time (20% to 80%) Fall time (80% to 20%) Output Impedance 50/75/HiZ K Ohms (single ended) Return loss (with package) 1, 2 Frequency 0.25 to 3.125 Gbps 0.25 to 3.125 Gbps 0.25 to 3.125 Gbps 0.25 to 3.125 Gbps -- -- -- -- -- Min. -- -- -- -- -- -- -- -- -- Typ. 1.25 1.4 1.0 1.2 0.8 70 70 50/75 HiZ 9 Max. -- -- -- -- -- -- -- -- -- Units V, p-p V, p-p V, p-p V, p-p V ps ps Ohms dB VTX-DIFF-P-P-1.25 Differential swing (1.25V setting)1, 2 1. All measurements are with 50 ohm impedance. 2. See technical note TN1124, LatticeECP2/M SERDES/PCS Usage Guide for actual binary settings and the min-max range. Table 3-8. Channel Output Jitter Description Deterministic Random Total Deterministic Random Total Deterministic Random Total Deterministic Random Total Frequency 3.125 Gbps 3.125 Gbps 3.125 Gbps 2.5Gbps 2.5Gbps 2.5Gbps 1.25 Gbps 1.25 Gbps 1.25 Gbps 250 Mbps 250 Mbps 250 Mbps Min. -- -- -- -- -- -- -- -- -- -- -- -- Typ. 0.08 0.22 0.33 0.05 0.17 0.24 0.03 0.10 0.15 0.04 0.12 0.15 Max. 0.12 0.38 0.43 0.11 0.30 0.39 0.11 0.18 0.29 0.17 0.13 0.29 Units UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p Note: Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock @ 10X mode. 3-38 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet Table 3-9. SERDES/PCS Latency Breakdown (Parallel Clock Cycle) Item Transmit Data Latency T1 T2 T3 T4 R1 R2 R3 R4 R5 R6 FPGA Bridge Transmit2 8b10b Encoder SERDES Bridge Transmit Serializer3 Deserializer3 SERDES Bridge Receive Word Alignment 8b10b Decoder Clock Tolerance Compensation FPGA Bridge Receive 2 Description Min. 1 2 2 Average 3 2 2 Max. 5 2 2 2.4 1.2 Bypass 1 1 1 Receive Data Latency 2 4 1 7 1 2 4 1 15 3 2 4 1 23 5 1 0 1 1 1 1. PCS internal Parallel Clock. This clock rate is same as the rxfullclk in table 8-6. 2. FPGA Bridge latency varies by UP/DOWN Sample FIFO read/write. These numbers were presented for 8bit/10bit interface. The depth of Down Sample/Up Sample FIFO is 4. The earliest read can be done after write clock cycle (1 clock) in Down Sample FIFO. The latest read will be done after the FIFO is full (4 + 1 = 5). For 16b/20b interface, the numbers become doubled. Min = 2, Max = 10. This latency depends on the internal FIFO flag operation. 3. The maximum latency applies to bit0. Bit1 latency = Bit0 latency + 1 UI. Bit2 latency = Bit0 latency + 2 UI. Figure 3-12. Transmitter and Receiver Block Diagram SERDES REFCLK SERDES Bridge Recovered Clock R3 WA PCS FPGA Bridge FPGA Core FPGA EBRD Clock R4 DEC Elastic Buffer FIFO BYPASS R5 R1 HDINPi HDINNi Receiver EQ CDR Deserializer 1:8/1:10 R2 Polarity Adjust R6 Down Sample FIFO Receive Data BYPASS BYPASS BYPASS FPGA Receive Clock REFCLK Transmit Clock TX PLL T2 T3 T4 HDOUTPi HDOUTNi Transmitter Serializer 8:1/10:1 Polarity Adjust Encoder T1 Up Sample FIFO Transmit Data BYPASS BYPASS BYPASS FPGA Transmit Clock 3-39 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet SERDES High Speed Data Receiver (LatticeECP2M Family Only) Table 3-10. Serial Input Data Specifications Symbol RX-CIDS VRX-DIFF-S VRX-IN VRX-CM-DC VRX-CM-AC ZRX-TERM RLRX-RL Description Stream of nontransitions (CID = Consecutive Identical Digits) @ 10-12 BER Differential input sensitivity Input levels Input common mode range (DC coupled) Input common mode range (AC coupled)3 Input termination 50/75 Ohm/High Z Return loss (without package) 100 0 0.5 0 -- -- -- 1 Min. Typ. 7 @ 3.125 Gbps 20 @ 1.25 Gbps -- -- -- -- -- 50 9 Max. Units Bits -- VCCRX + 0.8 1.2 1.5 3000 -- mV, p-p V V V Bits Ohms dB TRX-RELOCK CDR re-lock time2 1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling. 2. This is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded data. 3. AC coupling is used to interface to LVPECL and LVDS. Input Data Jitter Tolerance A receiver's ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface standards have recognized the dependency on jitter type and have recently modified specifications to indicate tolerance levels for different jitter types as they relate to specific protocols (e.g. FC, etc.). Sinusoidal jitter is considered to be a worst case jitter type. Table 3-11. Receiver Total Jitter Tolerance Specification1 Description Deterministic Random Total Deterministic Random Total Deterministic Random Total Deterministic Random Total 250 Mbps2 1.25 Gbps 2.5 Gbps Frequency Condition 600 mV differential eye 3.125 Gbps 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye 600 mV differential eye Min. -- -- -- -- -- -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. 0.54 0.26 0.80 0.61 0.22 0.81 0.53 0.22 0.80 0.42 0.10 0.60 Units UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p UI, p-p 1. Values are measured with PRBS 27-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal, room temperature. 2. Jitter specification is limited by measurement equipment capability. Table 3-12. Periodic Receiver Jitter Tolerance Specification1 Description Frequency 2.5 Gbps 1.25 Gbps 250 Mbps2 Condition 600 mV differential eye 600 mV differential eye 600 mV differential eye Min. -- -- -- -- Typ. -- -- -- -- Max. 0.20 0.22 0.20 0.08 Units UI, p-p UI, p-p UI, p-p UI, p-p 3.125 Gbps 600 mV differential eye Periodic 1. Values are measured with PRBS 27-1, all channels operating. 2. Jitter specification is limited by measurement equipment capability. 3-40 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet SERDES External Reference Clock (LatticeECP2M Family Only) The external reference clock selection and its interface are a critical part of system applications for this product. Table 3-13 specifies reference clock requirements, over the full range of operating conditions. Table 3-13. External Reference Clock Specification (refclkp/refclkn) Symbol FREF FREF-PPM VREF-IN-SE VREF-IN VREF-CM-DC VREF-CM-AC DREF TREF-R TREF-F ZREF-IN-TERM CREF-IN-CAP Description Frequency range Frequency tolerance Input swing, single-ended clock1 Input levels Input common mode range (DC coupled) Input common mode range (AC coupled) Duty cycle3 Rise time (20% to 80%) Fall time (80% to 20%) Input termination Input capacitance4 -- 2 Min. 25 -300 100 0 0.5 0 40 Typ. -- -- -- -- -- -- -- 500 500 50/2K -- Max. 320 300 1200 VCCP + 0.8 1.2 1.5 60 1000 1000 1.5 Units MHz ppm mV, p-p V V V % ps ps Ohms pF 1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same gain at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter. 2. When AC coupled, the input common mode range is determined by: (Min input level) + (Peak-to-peak input swing)/2 (Input common mode voltage) (Max input level) - (Peak-to-peak input swing)/2 3. Measured at 50% amplitude. 4. Input capacitance of 1.5pF is total capacitance, including both device and package. Figure 3-13. Jitter Transfer 5.00 0.00 Jitter T. Gain@25C,1.20V, PJ=100ps -5.00 dB -10.00 -15.00 -20.00 -25.00 0.1 1 Frequency (MHz) 10 100 Note: This graph is for a nominal device. SERDES Power-Down/Power-Up Specification Table 3-14. Power-Down and Power-Up Specification Symbol tPWRDN tPWRUP Description Power-down time after all power down register bits set to `0' Power-up time after all power down register bits set to `1' Max. 10 5 Units s ms 3-41 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet PCI Express Electrical and Timing Characteristics AC and DC Characteristics Table 3-15. Transmit1, 2 Symbol UI VTX-DIFF_P-P VTX-DE-RATIO VTX-CM-AC_P VTX-CM-DC-LINE-DELTA VTX-DC-CM ITX-SHORT ZTX-DIFF-DC TTX-RISE TTX-FALL LTX-SKEW TTX-EYE TTX-EYE-MEDIAN-TO-MAX-JITTER CTX 3 Description Unit interval Differential peak-to-peak output voltage De-emphasis differential output voltage ratio RMS AC peak common-mode output voltage Maximum Common mode voltage delta between n and p channels Tx DC common mode voltage Output short circuit current Differential output impedance Tx output rise time Tx output fall time Lane-to-lane static output skew for all lanes in port/link Transmitter eye width AC coupling capacitor Test Conditions Min 399.88 0.8 0 -- -- 0 Typ 400 1.0 -3.5 20 -- -- -- 100 -- -- -- -- -- -- Max 400.12 1.2 -7.96 -- 25 VCCOB + 5% 90 120 -- -- 1.3 -- 0.125 200 Units ps V dB mV mV V mA Ohms UI UI ns UI UI nF VTX-D+=0.0V VTX-D-=0.0V 20 to 80% 20 to 80% -- 80 0.125 0.125 -- 0.75 -- 75 1. Values are measured at 2.5 Gbps. 2. Compliant to PCI Express v1.1. 3. Measured at 60ps with plug-in board and jitter due to socket removed. Table 3-16. Receive Symbol UI VRX-DIFF_P-P VRX-IDLE-DET-DIFF_P-P ZRX-DIFF-DC ZRX-DC ZRX-HIGH-IMP-DC1 TRX-EYE TRX-EYE-MEDIAN-TO-MAX-JITTER Notes: 1. Measured with external AC-coupling on the receiver 2. Values are measured at 2.5 Gbps Description Unit Interval Differential peak-to-peak input voltage Idle detect threshold voltage DC differential input impedance DC input impedance Power-down DC input impedance Receiver eye width Test Conditions Min. 399.88 0.175 65 80 40 200K 0.4 -- Typ. 400 -- -- 100 50 -- -- -- Max. 400.12 -- 175 120 60 -- -- 0.3 Units ps V mV Ohms Ohms Ohms UI UI 3-42 Lattice Semiconductor Table 3-17. Reference Clock Symbol FREFCLK VCM TR/TF VSW DCREFCLK PPM Description Reference clock frequency Input common mode voltage Clock input rise/fall time Differential input voltage swing Input clock duty cycle Reference clock tolerance DC and Switching Characteristics LatticeECP2/M Family Data Sheet Test Conditions Min. -- -- -- 0.6 40 -300 Typ. 100 0.65 -- -- 50 -- Max. -- -- 1.0 1.6 60 +300 Units MHz V ns V % ppm 3-43 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter sysCONFIG Byte Data Flow tSUCBDI tHCBDI tCODO tSUCS tHCS tSUWD tHWD tDCB tCORD tBSCH tBSCL tBSCYC tSUSCDI tHSCDI tCODO tSSCH tSSCL tICFG tVMC tPRGMRJ tPRGM tDINIT tDPPINIT tDPPDONE tIODISS tIOENSS tMWC tCFGX tCSSPI tCSCCLK tSOCDO tSOE tCSPID fMAXSPI Byte D[0:7] Setup Time to CCLK Byte D[0:7] Hold Time to CCLK CCLK to DOUT in Flowthrough Mode CSN[0:1] Setup Time to CCLK CSN[0:1] Hold Time to CCLK Write Signal Setup Time to CCLK Write Signal Hold Time to CCLK CCLK to BUSY Delay Time CCLK to Out for Read Data Byte Slave CCLK Minimum High Pulse Byte Slave CCLK Minimum Low Pulse Byte Slave CCLK Cycle Time DI Setup Time to CCLK Slave Mode DI Hold Time to CCLK Slave Mode CCLK to DOUT in Flowthrough Mode Serial Slave CCLK Minimum High Pulse Serial Slave CCLK Minimum Low Pulse Minimum Vcc to INITN High Time from tICFG to Valid Master CCLK PROGRAMN Pin Pulse Rejection PROGRAMN Low Time to Start Configuration PROGRAMN High to INITN High Delay Delay Time from PROGRAMN Low to INITN Low Delay Time from PROGRAMN Low to DONE Low User I/O Disable from PROGRAMN Low User I/O Enabled Time from CCLK Edge During Wake-up Sequence Additional Wake Master Clock Signals after DONE Pin High INITN High to CCLK Low INITN High to CSSPIN Low CCLK Low before CSSPIN Low CCLK Low to Output Valid CSSPIN[0:1] Active Setup Time CSSPIN[0:1] Low to First CCLK Edge Setup Time Max. CCLK Frequency - SPI Flash Read Opcode (0x03) (SPIFASTN = 1) Max. CCLK Frequency - SPI Flash Fast Read Opcode (0x0B) (SPIFASTN = 0) 7 1 -- 7 1 7 1 -- -- 6 9 15 7 1 -- 6 6 -- -- -- 25 -- -- -- -- -- 120 -- -- 0 -- 300 300+3cyc -- -- -- -- 12 -- -- -- -- 12 12 -- -- -- -- -- 12 -- -- 28 2 8 -- 1 37 37 35 25 -- 1 2 -- 15 -- 600+6cyc 20 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms us ns ns ms ns ns ns ns cycles s us ns ns ns ns MHz MHz Description Min. Max. Units sysCONFIG Byte Slave Clocking sysCONFIG Serial (Bit) Data Flow sysCONFIG Serial Slave Clocking sysCONFIG POR, Initialization and Wake-up sysCONFIG SPI Port 3-44 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet LatticeECP2/M sysCONFIG Port Timing Specifications (Continued) Over Recommended Operating Conditions Parameter tSUSPI tHSPI Timing v.A 0.11 Description SOSPI Data Setup Time Before CCLK SOSPI Data Hold Time After CCLK Min. 7 2 Max. -- -- Units ns ns Parameter Master Clock Frequency Duty Cycle Timing v.A 0.11 Min. Selected value - 30% 40 Max. Selected value + 30% 60 Units MHz % Figure 3-14. sysCONFIG Parallel Port Read Cycle tBSCL tBSCYC tBSCH CCLK t SUCS tHCS CS1N CSN tSUWD t HWD WRITEN tDCB BUSY t CORD D[0:7] *n = last byte of read cycle. Byte 0 Byte 1 Byte 2 Byte n* Figure 3-15. sysCONFIG Parallel Port Write Cycle tBSCL tBSCH CCLK t SUCS tHCS CS1N CSN t SUWD t HWD WRITEN tDCB BUSY tSUCBDI t HCBDI Byte 0 Byte 1 Byte 2 Byte n* D[0:7] *n = last byte of write cycle. 3-45 Lattice Semiconductor Figure 3-16. sysCONFIG Slave Serial Port Timing tSSCL DC and Switching Characteristics LatticeECP2/M Family Data Sheet tSSCH CCLK (input) t SUSCDI tHSCDI DIN t CODO DOUT Figure 3-17. Power-On-Reset (POR) Timing VCC / VCCAUX / VCCIO81 INITN tICFG DONE t VMC CCLK 2 CFG[2:0] 3 Valid 1. Time taken from VCC, VCCAUX or VCCIO8, whichever is the last to cross the POR trip point. 2. Device is in a Master Mode (SPI, SPIm). 3. The CFG pins are normally static (hard wired). Figure 3-18. Configuration from PROGRAMN Timing tPRGMRJ PROGRAMN t DINIT INITN tDPPINIT DONE t DINITD CCLK CFG[2:0] 1 t IODISS Valid USER I/O 1. The CFG pins are normally static (hard wired) 3-46 Lattice Semiconductor Figure 3-19. Wake-Up Timing PROGRAMN DC and Switching Characteristics LatticeECP2/M Family Data Sheet INITN DONE Wake-Up tMWC CCLK tIOENSS USER I/O Figure 3-20. SPI/SPIm Configuration Waveforms Capture CR0 & CIB VCC PROGRAMN DONE INITN SPIFASTN CSSPI0N CSSPI1N 0 CCLK SISPI/BUSY SPID0 Opcode Address Ignore Valid Bitstream 1 2 3 ... 7 8 9 10 ... 31 32 33 34 ... 127 128 Capture CFGx and SPIFASTN 3-47 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet JTAG Port Timing Specifications Over Recommended Operating Conditions Symbol fMAX tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN Timing v.A 0.11 Parameter TCK clock frequency TCK [BSCAN] clock pulse width TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TCK [BSCAN] rise/fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to valid disable TAP controller falling edge of clock to valid enable BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to valid output BSCAN test update register, falling edge of clock to valid disable BSCAN test update register, falling edge of clock to valid enable Min -- 40 20 20 8 10 50 -- -- -- 8 25 -- -- -- Max 25 -- -- -- -- -- -- 10 10 10 -- -- 25 25 25 Units MHz ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns Figure 3-21. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH TCK tBTCPL tBTH tBTCP tBTCOEN TDO Valid Data tBTCO Valid Data tBTCODIS tBTCRS Data to be captured from I/O tBTUPOEN Data to be driven out to I/O tBTCRH Data Captured tBUTCO Valid Data tBTUODIS Valid Data 3-48 Lattice Semiconductor DC and Switching Characteristics LatticeECP2/M Family Data Sheet Switching Test Conditions Figure 3-23 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-18. Figure 3-22. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT R2 CL* Test Poi nt *CL Includes Test Fixture and Probe Capacitance Table 3-18. Test Fixture Required Components, Non-Terminated Interfaces Test Condition R1 R2 CL Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCIO/2 LVTTL and other LVCMOS settings (L -> H, H -> L) VT -- -- -- -- -- -- VCCIO -- VCCIO 1M 0pF LVCMOS 1.8 = VCCIO/2 LVCMOS 1.5 = VCCIO/2 LVCMOS 1.2 = VCCIO/2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) LVCMOS 2.5 I/O (H -> Z) LVCMOS 2.5 I/O (L -> Z) 1M VCCIO/2 VCCIO/2 VOH - 0.10 VOL + 0.10 100 100 Note: Output test conditions for all other interfaces are determined by the respective standards. 3-49 LatticeECP2/M Family Data Sheet Pinout Information August 2008 Data Sheet DS1006 Signal Descriptions Signal Name General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIC exists. When Edge is T (Top) or B (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number*]_[A/B] I/O [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with special function pins. These pins, when not used as special purpose pins, can be programmed as I/Os for user logic. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. GSRN NC GND VCC VCCAUX VCCIOx VCCPLL VREF1_x, VREF2_x XRES4 PLLCAP4 [LOC][num]_VCCPLL [LOC][num]_GPLL[T, C]_IN_A [LOC][num]_GPLL[T, C]_FB_A [LOC][num]_SPLL[T, C]_IN_A [LOC][num]_SPLL[T, C]_FB_A [LOC][num]_DLL[T, C]_IN_A [LOC][num]_DLL[T, C]_FB_A PCLK[T, C]_[n:0]_[3:0] I -- -- -- -- -- -- -- -- -- -- I I I I I I I Global RESET signal (active low). Any I/O pin can be GSRN. No connect. Ground. Dedicated pins. Power supply pins for core logic. Dedicated pins. Auxiliary power supply pin. This dedicated pin powers all the differential and referenced input buffers. Dedicated power supply pins for I/O bank x. PLL supply pins. Should be tied to VCC even when the corresponding PLL is unused. Reference supply pins for I/O bank x. Pre-determined pins in each bank are assigned as VREF inputs. When not used, they may be used as I/O pins. 10K ohm +/-1% resistor must be connected between this pad and ground. External capacitor connection for PLL. Power supply pin for PLL: ULM, LLM, URM, LRM, num = row from center. General Purpose PLL (GPLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. Optional feedback GPLL input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. Secondary PLL (SPLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. Optional feedback (SPLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. DLL input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. Optional feedback (DLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. Primary Clock pads, T = true and C = complement, n per side, indexed by bank and 0,1,2,3 within bank. I/O Description PLL, DLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins) (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1006 Pinout Information_01.9 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet Signal Descriptions (Cont.) Signal Name [LOC]DQS[num] [LOC]DQ[num] I/O I/O I/O Description DQ input/output pads: T (top), R (right), B (bottom), L (left), DQS, num = ball function number. DQ input/output pads: T (top), R (right), B (bottom), L (left), DQ, associated DQS number. Test Mode Select input, used to control the 1149.1 state machine. Pull-up is enabled during configuration. Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled. Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Pull-up is enabled during configuration. Output pin. Test Data Out pin used to shift data out of a device using 1149.1. Power supply pin for JTAG Test Access Port. Mode pins used to specify configuration mode values latched on rising edge of INITN. During configuration, a pull-up is enabled. These are dedicated pins. Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. It is a dedicated pin. Initiates configuration sequence when asserted low. This pin always has an active pull-up. This is a dedicated pin. Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. This is a dedicated pin. Configuration Clock for configuring an FPGA in sysCONFIG mode. Read control command in SPI or SPIm mode. sysCONFIG chip select (active low). During configuration, a pull-up is enabled. sysCONFIG chip select (active low). During configuration, a pull-up is enabled. Write Data on Parallel port (active low). sysCONFIG Port Data I/O for Parallel mode. D[0]/SPIFASTN D[1:6] D[7]/SPID0 DOUT/CSON DI/CSSPI0N Dedicated SERDES Signals1, 2, 3 [LOC]_SQ_VCCAUX33 [LOC]_SQ_REFCLKN [LOC]_SQ_REFCLKP [LOC]_SQ_VCCP -- I I -- Termination resistor switching power (3.3V). This pin must be tied to 3.3V even if the quad is unused. Negative Reference Clock Input Positive Reference Clock Input PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V even if the quad is unused. I/O I/O I/O O I/O sysCONFIG Port Data I/O for SPI or SPIm. When using the SPI or SPIm mode, this pin should either be tied high or low, must not be left floating. sysCONFIG Port Data I/O for Parallel sysCONFIG Port Data I/O for Parallel, SPI, SPIm Output for serial configuration data (rising edge of CCLK) when using sysCONFIG port. Input for serial configuration data (clocked with CCLK) when using sysCONFIG port. During configuration, a pull-up is enabled. Output when used in SPI/ SPIm modes. Test and Programming (Dedicated Pins) TMS TCK I I TDI I TDO VCCJ O -- Configuration Pads (Used During sysCONFIG) CFG[2:0] INITN PROGRAMN DONE CCLK BUSY/SISPI CSN CS1N WRITEN I I/O I I/O I/O I/O I I I 4-2 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet Signal Descriptions (Cont.) Signal Name [LOC]_SQ_VCCIBm [LOC]_SQ_VCCOBm [LOC]_SQ_HDOUTNm [LOC]_SQ_HDOUTPm [LOC]_SQ_HDINNm [LOC]_SQ_HDINPm [LOC]_SQ_VCCTXm4 [LOC]_SQ_VCCRXm4 I/O -- -- O O I I -- -- Description Input buffer power supply, channel m (1.2V/1.5V). This pin should be left floating if the channel is unused. Output buffer power supply, channel m (1.2V/1.5V). This pin should be left floating if the channel is unused. High-speed output, negative channel m High-speed output, positive channel m High-speed input, negative channel m High-speed input, positive channel m Transmitter power supply, channel m (1.2V). This pin must be tied to 1.2V even if the channel is unused. Receiver power supply, channel m (1.2V). This pin must be tied to 1.2V even if the channel is unused. 1. These signals are relevant for LatticeECP2M family. 2. m defines the associated channel in the Quad. 3. These signals are defined in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower left), LRC (lower right). 4. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage, care must be given. For more information, refer to technical note TN1159, LatticeECP2/M Pin Assignment Recommendations. 4-3 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe PIO Within PIC A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B DDR Strobe (DQS) and Data (DQ) Pins DQ DQ DQ DQ DQ DQ DQ DQ [Edge]DQSn DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ [Edge]DQSn DQ DQ DQ DQ DQ DQ DQ DQ DQ For Left and Right Edges of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] For Bottom Edge of the Device P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] P[Edge] [n+4] Notes: 1. "n" is a row PIC number. 2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits of data for the left and right edges and up to 17 bits of data for the bottom edge. In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the "Signal Names" column of the Signal Descriptions table. 4-4 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 LFE2-6 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Non Configuration VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 VCCIO Bank4 Bank5 Bank6 Bank7 Bank8 GND, GND0 to GND7 NC Bank0 Bank1 Bank2 Single Ended/ Differential I/O Pairs per Bank (including emulated with resistors) Bank3 Bank4 Bank5 Bank6 Bank7 Bank8 Bank0 (Top Edge) Bank1 (Top Edge) Bank2 (Right Edge) Bank3 (Right Edge) True LVDS I/O Pairs per Bank Bank4 (Bottom Edge) Bank5 (Bottom Edge) Bank6 (Left Edge) Bank7 (Left Edge) Bank8 (Right Edge) Muxed Pins Dedicated Pins 144 TQFP 90 43 5 14 7 34 3 10 4 0 1 1 1 1 1 1 1 1 1 12 4 8/4 17/8 4/2 8/4 18/9 8/4 9/4 12/6 6/2 0 0 1 3 0 0 2 5 0 256 fpBGA 190 95 5 14 7 54 3 7 4 0 2 2 2 2 2 2 2 2 1 20 3 18/6 34/17 20/10 12/6 32/16 14/7 26/13 20/10 14/7 0 0 5 3 0 0 7 5 0 144 TQFP 93 45 5 14 7 33 3 10 4 0 1 1 1 1 1 1 1 1 1 12 1 8/4 18/9 4/2 8/4 18/9 10/5 9/4 12/6 6/2 0 0 1 3 0 0 2 5 0 LFE2-12 208 PQFP 131 62 5 14 7 40 3 14 8 0 2 2 2 2 2 2 2 2 2 22 0 18/9 18/9 11/5 11/5 19/9 18/9 18/8 12/6 6/2 0 0 4 3 0 0 6 5 0 256 fpBGA 193 96 5 14 7 54 3 7 4 0 2 2 2 2 2 2 2 2 1 20 0 18/9 34/17 20/10 12/6 32/16 17/8 26/13 20/10 14/7 0 0 5 3 0 0 7 5 0 484 fpBGA 297 148 5 14 7 57 3 16 16 0 4 4 4 4 4 4 4 4 2 60 44 50/25 46/23 24/12 16/8 46/23 46/23 32/16 23/11 14/7 0 0 6 4 0 0 8 5 0 4-5 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 (Cont.) LFE2-6 Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 144 TQFP 0 0 0 0 0 0 0 0 0 0 0 0 0 18 8 0 0 0 256 fpBGA 0 0 1 0 2 1 1 1 0 0 0 0 0 32 14 0 0 0 144 TQFP 0 0 0 0 0 0 0 0 0 0 0 0 0 18 10 0 0 0 LFE2-12 208 PQFP 0 0 0 0 0 0 0 0 0 0 0 0 0 19 18 0 0 0 256 fpBGA 0 0 1 0 2 1 1 1 0 0 0 0 0 32 17 0 0 0 484 fpBGA 0 0 1 0 3 3 1 1 0 0 0 0 0 46 46 0 0 0 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). 4-6 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 LFE2-20 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Non Configuration VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 VCCIO Bank4 Bank5 Bank6 Bank7 Bank8 GND, GND0 to GND7 NC Bank0 Bank1 Bank2 Single Ended/ Differential I/O Pairs per Bank (including emulated with resistors) Bank3 Bank4 Bank5 Bank6 Bank7 Bank8 Bank0 (Top Edge) Bank1 (Top Edge) Bank2 (Right Edge) Bank3 (Right Edge) True LVDS I/O Pairs per Bank Bank4 (Bottom Edge) Bank5 (Bottom Edge) Bank6 (Left Edge) Bank7 (Left Edge) Bank8 (Right Edge) Muxed Pins Dedicated Pins 208 PQFP 131 62 5 14 7 42 3 14 8 0 2 2 2 2 2 2 2 2 2 22 0 18/9 18/9 11/5 11/5 19/9 18/9 18/8 12/6 6/2 0 0 4 3 0 0 6 5 0 256 fpBGA 193 96 5 14 7 54 3 7 4 0 2 2 2 2 2 2 2 2 1 20 1 18/9 34/17 20/10 12/6 32/16 17/8 26/13 20/10 14/7 0 0 5 3 0 0 7 5 0 484 fpBGA 331 165 5 14 7 60 3 18 16 0 4 4 4 4 4 4 4 4 2 60 8 50/25 46/23 34/17 22/11 46/23 46/23 40/20 33/16 14/7 0 0 9 5 0 0 10 8 0 672 fpBGA 402 200 5 14 7 64 3 24 16 0 5 5 5 5 5 5 5 5 2 72 101 67/33 52/26 36/18 32/16 50/25 68/34 48/24 35/17 14/7 0 0 9 8 0 0 12 8 0 LFE2-35 484 fpBGA 331 165 5 14 7 60 3 16 16 2 4 4 4 4 4 4 4 4 2 60 8 50/25 46/23 34/17 22/11 46/23 46/23 40/20 33/16 14/7 0 0 9 5 0 0 10 8 0 672 fpBGA 450 224 5 14 7 68 3 22 16 2 5 5 5 5 5 5 5 5 2 72 102 67/33 52/26 48/24 42/21 54/27 68/34 58/29 47/23 14/7 0 0 12 9 0 0 13 11 0 4-7 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 (Cont.) LFE2-20 Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 1 Bank Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 208 PQFP 0 0 0 0 0 0 0 0 0 0 0 0 0 19 18 0 0 0 256 fpBGA 0 0 1 0 2 1 1 1 0 0 0 0 0 32 17 0 0 0 484 fpBGA 0 0 2 0 3 3 2 2 0 0 0 0 0 46 46 0 0 0 672 fpBGA 0 0 2 2 3 4 3 2 0 0 0 0 0 50 68 0 0 0 LFE2-35 484 fpBGA 0 0 2 0 3 3 1 2 0 0 0 0 0 46 46 0 0 0 672 fpBGA 0 0 3 2 3 4 3 3 0 0 0 0 0 54 68 0 0 0 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). 4-8 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 LFE2-50 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Non Configuration VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 VCCIO Bank4 Bank5 Bank6 Bank7 Bank8 GND, GND0 to GND7 NC Bank0 Bank1 Bank2 Single Ended/ Differential I/O Pairs per Bank (including emulated with resistors) Bank3 Bank4 Bank5 Bank6 Bank7 Bank8 Bank0 (Top Edge) Bank1 (Top Edge) Bank2 (Right Edge) Bank3 (Right Edge) True LVDS I/O Pairs per Bank Bank4 (Bottom Edge) Bank5 (Bottom Edge) Bank6 (Left Edge) Bank7 (Left Edge) Bank8 (Right Edge) Muxed Pins Dedicated Pins 484 fpBGA 339 169 5 14 7 68 3 16 16 4 4 4 4 4 4 4 4 4 2 60 0 50/25 46/23 38/19 22/11 46/23 46/23 40/20 37/18 14/7 0 0 9 5 0 0 10 8 0 672 fpBGA 500 249 5 14 7 79 3 20 16 4 5 5 5 5 5 5 5 5 2 72 3 67/33 66/33 56/28 48/24 62/31 68/34 64/32 55/27 14/7 0 0 13 12 0 0 16 12 0 500 249 5 14 7 79 3 20 16 2 5 5 5 5 5 5 5 5 2 72 5 67/33 66/33 56/28 48/24 62/31 68/34 64/32 55/27 14/7 0 0 13 12 0 0 16 12 0 LFE2-70 672 fpBGA 900 fpBGA 583 290 5 14 7 89 3 26 17 4 6 6 6 6 6 6 6 6 2 104 101 84/42 76/38 74/37 48/24 72/35 80/40 64/32 71/35 14/7 0 0 18 12 0 0 16 16 0 4-9 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 (Cont.) LFE2-50 Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank4 Bank1 Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 484 fpBGA 0 0 2 0 3 3 1 2 0 0 0 0 0 46 46 0 0 0 672 fpBGA 0 0 3 3 4 4 4 3 0 0 0 0 0 62 68 0 0 0 0 0 3 3 4 4 4 3 0 0 0 0 0 62 68 0 0 0 LFE2-70 672 fpBGA 900 fpBGA 0 0 4 3 4 5 4 4 0 0 0 0 0 72 80 0 0 0 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). 4-10 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 LFE2M20 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Non Configuration VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 VCCIO Bank4 Bank5 Bank6 Bank7 Bank8 GND, GND0 to GND7 NC Bank0 Bank1 Bank2 Single Ended/ Differential I/O Bank3 Pairs per Bank (including Bank4 emulated with resistors) Bank5 Bank6 Bank7 Bank8 Bank0 (Top Edge) Bank1 (Top Edge) Bank2 (Right Edge) Bank3 (Right Edge) True LVDS I/O Pairs per Bank Bank4 (Bottom Edge) Bank5 (Bottom Edge) Bank6 (Left Edge) Bank7 (Left Edge) Bank8 (Right Edge) Muxed Pins Dedicated Pins 140 70 5 14 7 64 3 6 4 1 1 1 2 2 2 2 2 2 1 22 17 0/0 0/0 14/7 16/8 32/16 20/10 16/8 28/14 14/7 0 0 3 4 0 0 4 7 0 304 152 5 14 7 84 3 16 8 4 4 3 4 4 4 4 4 4 2 57 11 36/18 18/9 30/15 36/18 62/31 28/14 40/20 40/20 14/7 0 0 7 9 0 0 10 10 0 140 70 5 14 7 60 3 6 4 1 1 1 2 2 2 2 2 2 1 22 17 0/0 0/0 14/7 16/8 32/16 20/10 16/8 28/14 14/7 0 0 3 4 0 0 4 7 0 LFE2M35 303 151 5 14 7 84 3 16 8 4 4 3 4 4 4 4 4 4 2 57 12 36/18 18/9 30/15 36/18 62/31 28/14 39/19 40/20 14/7 0 0 7 9 0 0 10 10 0 410 199 5 14 7 89 3 29 17 8 5 4 5 5 4 5 5 5 2 80 37 63/31 18/9 50/25 43/21 50/21 60/30 52/25 60/30 14/7 0 0 12 11 0 0 14 15 0 256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA 4-11 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 (Cont.) LFE2M20 Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per Bank4 I/O Bank1 Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 0 0 0 0 2 1 0 1 0 0 0 0 0 32 20 16 28 0 0 0 1 1 4 2 3 2 0 0 0 0 0 62 28 40 40 0 0 0 0 0 2 1 0 1 0 0 0 0 0 32 20 16 28 0 LFE2M35 0 0 1 1 4 2 1 2 0 0 0 0 0 62 28 39 40 0 0 0 3 2 3 3 2 3 0 0 0 0 0 50 60 52 60 0 256 fpBGA 484 fpBGA 256 fpBGA 484 fpBGA 672 fpBGA 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). 4-12 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 LFE2M50 Pin Type Single Ended User I/O Differential Pair User I/O TAP Pins Configuration Muxed Pins Dedicated Pins (Non TAP) Non Configuration VCC VCCAUX VCCPLL Bank0 Bank1 Bank2 Bank3 VCCIO Bank4 Bank5 Bank6 Bank7 Bank8 GND, GND0 to GND7 NC Bank0 Bank1 Bank2 Single Ended/ Differential Bank3 I/O Pairs per Bank (includ- Bank4 ing emulated with resistors) Bank5 Bank6 Bank7 Bank8 Bank0 (Top Edge) Bank1 (Top Edge) Bank2 (Right Edge) Bank3 (Right Edge) True LVDS I/O Pairs per Bank Bank4 (Bottom Edge) Bank5 (Bottom Edge) Bank6 (Left Edge) Bank7 (Left Edge) Bank8 (Right Edge) Muxed Pins Dedicated Pins 270 135 5 14 7 69 3 16 8 4 4 3 4 4 4 4 4 4 2 57 31 36/18 18/9 30/15 36/18 42/21 28/14 40/20 40/20 0/0 0 0 7 9 0 0 10 10 0 372 185 5 14 7 72 3 20 26 8 5 4 5 5 4 5 5 5 2 80 35 63/31 18/9 50/25 43/21 24/12 60/30 54/27 60/30 0/0 0 0 12 11 0 0 14 15 0 410 205 5 14 7 72 3 62 18 4 6 6 9 9 6 6 9 9 2 122 121 56/28 36/18 54/27 44/22 38/19 58/29 60/30 64/32 0/0 0 0 13 11 0 0 15 17 0 416 208 5 14 7 75 3 44 16 4 6 6 9 9 6 6 9 9 2 122 63 34/17 42/21 70/35 60/30 38/19 40/20 62/31 70/35 0/0 0 0 17 15 0 0 15 17 0 LFE2M70 436 218 5 14 7 76 3 44 12 4 7 7 9 9 7 7 9 9 2 134 283 46/23 34/17 72/36 64/32 40/20 40/20 66/33 74/37 0/0 0 0 18 16 0 0 16 18 0 LFE2M100 416 207 5 14 7 74 3 44 16 4 6 6 9 9 6 6 9 9 2 122 63 34/17 42/21 70/35 60/30 38/19 40/20 62/31 70/35 0/0 0 0 17 15 0 0 15 17 0 520 260 5 14 7 78 3 44 12 4 7 7 9 9 7 7 9 9 2 134 199 54/27 44/22 80/40 80/40 44/22 46/23 82/41 90/45 0/0 0 0 20 20 0 0 20 22 0 484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA 4-13 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100 (Cont.) LFE2M50 Pin Type Bank0 Bank1 Bank2 Bank3 Available DDR-Interfaces per I/O Bank1 Bank4 Bank5 Bank6 Bank7 Bank8 Bank0 Bank1 Bank2 Bank3 PCI Capable I/Os per Bank Bank4 Bank5 Bank6 Bank7 Bank8 0 0 2 2 3 2 1 3 0 0 0 0 0 50 60 52 60 0 0 0 4 3 1 3 3 4 0 0 0 0 0 24 60 54 60 0 0 0 2 1 3 3 2 3 0 0 0 0 0 48 50 60 68 0 0 0 4 3 3 2 3 4 0 0 0 0 0 48 40 62 70 0 LFE2M70 0 0 4 4 3 3 4 4 0 0 0 72 64 40 40 66 74 0 0 0 4 3 3 2 3 4 0 0 0 0 0 48 40 62 70 0 LFE2M100 0 0 4 5 3 3 5 5 0 0 0 80 80 44 46 82 90 0 484 fpBGA 672 fpBGA 900 fpBGA 900 fpBGA 1152 fpBGA 900 fpBGA 1152 fpBGA 1. Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + 1 DM + Bank VREF1). 4-14 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet Available Device Resources by Package, LatticeECP2 Resource Device ECP2-6 ECP2-12 PLL/DLL ECP2-20 ECP2-35 ECP2-50 ECP2-70 256 fpBGA 4 4 4 -- -- -- 484 fpBGA -- 4 4 4 6 -- 672 fpBGA -- -- 4 4 6 8 900 fpBGA -- -- -- -- -- 8 Available Device Resources by Package, LatticeECP2M Resource Device ECP2M20 ECP2M35 PLL/DLL ECP2M50 ECP2M70 ECP2M100 256 fpBGA 10 10 -- -- -- 484 fpBGA 10 10 10 -- -- 672 fpBGA -- 10 10 -- -- 900 fpBGA -- -- 10 10 10 1152 fpBGA -- -- -- 10 10 4-15 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Power Supply and NC Signals VCC 144 TQFP3 16, 22, 29, 48, 54, 83, 94, 102, 128, 135 208 PQFP3 256 fpBGA4 484 fpBGA4 LFE2-12/LFE2-20: N6, N18, J10, J11, J12, J13, K14, K9, L14, L9, M14, M9, N14, N9, P10, P11, P12, P13 LFE2-35/LFE2-50: J10, J11, J12, J13, K14, K9, L14, L9, M14, M9, N14, N9, P10, P11, P12, P13 G10, G9, H8, H9 G11, G12, G13, G14 H14, H15, J15, K16 L16, M16, N16, P16 R14, T12, T13, T14 R9, T10, T11, T9 N7, P7, P8, R8 J8, K7, L7, M7 P15, R15 T8 G5, K5, R5, V7, V11, V8, V13, V15, M17, P17, E17, G18, D11, F13, C5, E6 LFE2-12/LFE2-20: None LFE2-35: N6, N18 LFE2-50: N6, N18, K6, J16 GND 1 12, 19, 28, 40, 74, 80, LFE2-6: G7, G9, G10, 97, 116, 129, 140, 146, H7, J10, K10, K8 171, 188, 198 LFE2-12/LFE2-20: G7, G9, G10, H7, J10, K10, K8 VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCJ VCCAUX 139 117 106 89 64 42 31 9 85 35 6, 39, 90, 142 195, 206 162, 170 143, 148 123, 135 93, 100 55, 63 38, 44 10, 14 113, 118 51 C5, E7 C12, E10 E14, G12 K12, M14 M10, P12 M7, P5 K5, M3 E3, G5 T15 K7 7, 30, 70, 86, 125, 151, G8, H10, J7, K9 174, 190 None None VCCPLL None 11, 21, 30, 47, 51, 61, 81, 95, 105, 120, 133, 138 5, 13, 17, 25, 32, 42, 60, 68, 77, 81, 89, 102, 115, 122, 139, 145, 159, 169, 175, 184, 192, 201 A1, A16, B12, B5, C8, E15, E2, H14, H8, H9, J3, J8, J9, M15, M2, P9, R12, R5, T1, T16 A22, AA19, AA4, AB1, AB22, B19, B4, C14, C9, D2, D21, F17, F6, H10, H11, H12, H13, J14, J20, J3, J9, K10, K11, K12, K13, K15, K8, L10, L11, L12, L13, L15, L8, M10, M11, M12, M13, M15, M8, N10, N11, N12, N13, N15, N8, P14, P20, P3, P9, R10, R11, R12, R13, U17, U6, W2, W21, Y14, Y9, A1 LFE2-12: E3, F3, F1, H4, F2, H5, G1, G3, G2, G4, K6, N1, M2, N2, M1, N3, N5, N4, P5, N19, M19, J22, L22, H22, K22, J16, D22, F21, E21, E22, H19, G20, G19, F20, C21, C22, H6, J6, H3, H2, H17, H16, H20, H18 LFE2-20/LFE2-35: K6, J16, H6, J6, H3, H2, H17, H16, H20, H18 LFE2-50: None NC2 LFE2-6: 45, 46, 124, 127 LFE2-12: 127 None LFE2-6: K6, R3, P4 LFE2-12/LFE2-20: None 1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Pin orientation follows the conventional order from the pin 1 marking of the top side view and counter-clockwise. 4. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 4-16 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2 Power Supply and NC (Cont.) Signals VCC 672 fpBGA3 900 fpBGA3 LFE2-20: R8, P18, M8, L20, L12, L13, L14, L15, AA11, AA20, K11, K21, K22, L11, L12, L13, L18, L19, L20, M11, M12, M15, M16, N11, N16, P11, P16, R11, M11, M20, N11, N20, V11, V20, W11, W20, Y10, Y11, Y12, R12, R15, R16, T12, T13, T14, T15 Y13, Y18, Y19, Y20 LFE2-35/LFE2-50: L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, T14, T15 LFE2-70: L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, T14, T15 D11, D6, G9, J12, K12 D16, D21, G18, J15, K15 F23, J20, L23, M17, M18 AA23, R17, R18, T23, V20 AC16, AC21, U15, V15, Y18 AC11, AC6, U12, V12, Y9 AA4, R10, R9, T4, V7 F4, J7, L4, M10, M9 AE25, V18 AB5 J13, J14, K12, K13, K14, K15 J17, J18, J20, K17, K18, K20 L21, M21, M22, N21, N22, R21 U21, U22, V21, V22, W21, Y22 AA16, AA17, AA18, AA19, AB17, AB18 AA12, AA13, AA14, AB12, AB13, AB14 U10, U9, V10, W10, W9, Y9 L10, L9, M10, N10, P10, R10 AA21, Y21 AD3 VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCJ VCCAUX VCCPLL J10, J11, J16, J17, K18, L18, T18, U18, V16, V17, AA15, AB11, AB19, AB20, J11, J12, J19, K19, L22, M9, V10, V11, T9, U9, K9, L9 N9, P21, P9, T10, T21, V9, W22 LFE2-20: None LFE2-35/LFE2-70: R8, P18 LFE2-50: R8, P18, M8, L20 A2, A25, AA18, AA24, AA3, AA9, AD11, AD16, AD21, AD6, AE1, AE26, AF2, AF25, B1, B26, C11, C16, C21, C6, F18, F24, F3, F9, J13, J14, J21, J6, K10, K11, K13, K14, K16, K17, L10, L11, L16, L17, L24, L3, M13, M14, N10, N12, N13, N14, N15, N17, P10, P12, P13, P14, P15, P17, R13, R14, T10, T11, T16, T17, T24, T3, U10, U11, U13, U14, U16, U17, V13, V14, V21, V6 P22, P8, T22, Y7 GND1 A1, A30, AC28, AC3, AH13, AH18, AH23, AH28, AH3, AH8, AK1, AK30, C13, C18, C23, C28, C3, C8, H28, H3, L14, L15, L16, L17, M12, M13, M14, M15, M16, M17, M18, M19, N12, N13, N14, N15, N16, N17, N18, N19, N28, N3, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, U11, U12, U13, U14, U15, U16, U17, U18, U19, U20, V12, V13, V14, V15, V16, V17, V18, V19, V28, V3, W12, W13, W14, W15, W16, W17, W18, W19, Y14, Y15, Y16, Y17 A2, A3, A4, A5, AB28, AC4, AD23, AE1, AE2, AE29, AE3, AE30, AE4, AE5, AE6, AF1, AF2, AF23, AF26, AF27, AF28, AF29, AF3, AF30, AF4, AF5, AG1, AG13, AG16, AG18, AG2, AG26, AG27, AG28, AG29, AG3, AG30, AG4, AG8, AH1, AH16, AH2, AH26, AH27, AH29, AH30, AH4, AJ1, AJ2, AJ27, AJ28, AJ29, AJ3, AJ30, AK2, AK27, AK28, AK29, AK3, B1, B2, B3, B30, B4, B5, C1, C2, C29, C30, C4, D13, D18, D23, D28, D29, D3, D30, D4, E25, E26, E27, E28, E29, E3, E30, E4, E5, E6, F25, F5, F6, G6, G7, K10, K9, N27, N4, R1, R2, V27, V4 NC2 LFE2-20: E4, E3, E2, E1, H6, H5, F2, F1, H8, J9, G4, G3, K3, K2, K1, L2, L1, M2, M1, N2, T1, T2, P8, P6, P5, P4, U1, V1, P3, R3, R4, U2, V2, W2, T6, R5, AA19, W17, Y19, Y17, AF20, AE20, AA20, W18, AD20, AE21, AF21, AF22, R22, T21, P26, P25, R24, R23, P20, R19, P21, P19, P23, P22, N22, R21, N26, N25, J26, J25, J23, K23, H26, H25, H24, H23, F22, E24, D25, C25, D24, B25, H21, G22, B24, C24, D23, C23, E19, C19, B21, B20, D19, B19, G17, E18, G19, F17, A20, A19, E17, D18, M3, N6, P24 LFE2-35: K3, K2, K1, L2, L1, M2, M1, N2, M8, P3, R3, R4, U2, V2, W2, AF20, AE20, AA20, W18, AD20, AE21, AF21, AF22, P26, P25, R24, R23, P20, R19, L20, J26, J25, J23, K23, H26, H25, H24, H23, E19, C19, B21, B20, D19, B19, G17, E18, G19, F17, A20, A19, E17, D18, M3, N6, P24 LFE2-50: N6, P24, M3 LFE2-70: M8, L20, M3, P24, N6 1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 4-17 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Power Supply and NC Signal VCC VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCJ VCCAUX VCCPLL SERDES Power3 GND1 256 fpBGA G7, G9, H7, J10, K10, K8 E7 E10 E14, G12 K12, M14 M10, P12 M7, P5 K5, M3 E3, G5 T15 K7 G8, H10, J7, K9 G10 C15, B15, C12, A12, C11, C10, C14, C13, B9, C9, C5, C4, C8, C7, A6, C6, B3, C3 A1, A15, A16, A3, A9, B12, B6, E15, E2, H14, H8, H9, J3, J8, J9, M15, M2, P9, R12, R5, T1, T16 484 fpBGA J10, J11, J12, J13, K14, K9, L14, L9, M14, M9, N14, N9, P10, P11, P12, P13 B5, B9, E7, H9 D13, E16, H14 E21, G18, J15, K19 N19, P15, T18, V21 AA18, R14, V16, W13 AA5, R9, V7, W10 N4, P8, T5, V2 E2, G5, J8, K4 AA22, U19 W4 H11, H12, L15, L8, M15, M8, R11, R12 R8, H15, H8, R15 C22, B22, C19, A19, C18, C17, C21, C20, B16, C16, C12, C11, C15, C14, A13, C13, B10, C10 A1, A10, A16, A22, AA19, AA4, AB1, AB22, B13, B19, B4, D16, D2, D21, D7, G19, G4, H10, H13, J14, J9, K10, K11, K12, K13, K15, K20, K3, K8, L10, L11, L12, L13, M10, M11, M12, M13, N10, N11, N12, N13, N15, N20, N3, N8, P14, P9, R10, R13, T19, T4, W16, W2, W21, W7, Y10, Y13 NC2 D10, D11, D12, D13, D14, D4, D5, D6, D7, E11, LFE2M20: D14, D15, E14, E15, F13, F14, F15, G12, E6, E8, E9, F10, F7, F8, F9 G13, G14, G15 LFE2M35: D14, D15, E14, E15, F13, F14, F15, G12, G13, G14, G15, U6 LFE2M50: Y15, W15, AB20, AB21, AA20, AB19, AB18, Y22, Y21, Y17, Y18, Y16, W17, Y19, Y20, W19, W18, V17, V18, D15, G14, G15, D14, E15, E14, F15, F14, F13, G12, G13 1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 2. NC pins should not be connected to any active signals, VCC or GND. 3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks. Specifically, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices using the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details. 4-18 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Power Supply and NC (Cont.) Signal VCC 672 fpBGA LFE2M35: AD13, AD14, AD16, AD17, AD19, AD21, AD22, AD24, AD25, L12, L13, L14, L15, M11, M12, M15, M16, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, T14, T15 900 fpBGA LFE2M50: AH1, AH4, AH5, AH2, AH7, AH12, AH9, AH10, AH13, C13, C10, C9, C12, C7, C2, C5, C4, C1, L12, L13, L18, L19, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, N11, N12, N19, N20, P12, P19, R12, R19, T12, T19, U12, U19, V11, V12, LFE2M50: L12, L13, L14, L15, M11, M12, M15, M16, V19, V20, W11, W12, W13, W14, W15, W16, W17, N11, N16, P11, P16, R11, R12, R15, R16, T12, T13, W18, W19, W20, Y12, Y13, Y18, Y19 T14, T15 LFE2M70/LFE2M100: L12, L13, L18, L19, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, N11, N12, N19, N20, P12, P19, R12, R19, T12, T19, U12, U19, V11, V12, V19, V20, W11, W12, W13, W14, W15, W16, W17, W18, W19, W20, Y12, Y13, Y18, Y19 B12, B7, F11, J13, K12 D18, F16, J14, K15 G25, L21, M17, M25, N18 P18, R17, R25, T21, Y25 AA16, AC18, U15, V14 AA11, AE12, AE7, U12, V13 P9, R10, R2, T6, Y2 G2, L6, M10, M2, N9 AC24, U17 AA7 LFE2M35: AE19, J11, J12, J15, J16, L18, L9, M18, M9, R18, R9, T18, T9, V11, V12, V15, V16 LFE2M50: J11, J12, J15, J16, L18, L9, M18, M9, R18, R9, T18, T9, V11, V12, V15, V16 D14, E6, E9, F12, K12, K13 D17, E22, E25, F19, K18, K19 F28, J25, K28, M21, M24, N21, N28, P21, R25 AA28, AB25, AE28, T25, U21, V21, V28, W21, W24 AA18, AA19, AE19, AF22, AG17, AG25 AA12, AA13, AE12, AF9, AG14, AG6 AA3, AB6, AE3, T6, U10, V10, V3, W10, W7 F3, J6, K3, M10, M7, N10, N3, P10, R6 AA25, AD28 AG1 LFE2M50: AJ7, B7, AA10, AA11, AA20, AA21, K10, K11, K20, K21, L10, L11, L20, L21, Y10, Y11, Y20, Y21 LFE2M70/LFE2M100: AA10, AA11, AA20, AA21, K10, K11, K20, K21, L10, L11, L20, L21, Y10, Y11, Y20, Y21 N13, N18, V13, V18 VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCJ VCCAUX VCCPLL H7, K6, P7, R8, V18, P20, J17, G19 SERDES Power3 LFE2M35: C25, B25, C22, A22, C21, C20, C24, C23, LFE2M50: AH18, AJ18, AH21, AK21, AH22, AH23, B19, C19, C15, C14, C18, C17, A16, C16, B13, C13 AH19, AH20, AH24, AJ24, AH28, AH29, AH25, AH26, AK27, AH27, AJ30, AH30, C30, B30, C27, LFE2M50: AD13, AE13, AD16, AF16, AD17, AD18, A27, C26, C25, C29, C28, B24, C24, C20, C19, C23, AD14, AD15, AD19, AE19, AD23, AD24, AD20, C22, A21, C21, B18, C18 AD21, AF22, AD22, AE25, AD25, C25, B25, C22, A22, C21, C20, C24, C23, B19, C19, C15, C14, C18, LFE2M70/LFE2M100: C13, B13, C10, A10, C9, C8, C17, A16, C16, B13, C13 C12, C11, B7, C7, C3, C2, C6, C5, A4, C4, B1, C1, C30, B30, C27, A27, C26, C25, C29, C28, B24, C24, C20, C19, C23, C22, A21, C21, B18, C18, AH18, AJ18, AH21, AK21, AH22, AH23, AH19, AH20, AH24, AJ24, AH28, AH29, AH25, AH26, AK27, AH27, AJ30, AH30, AH1, AJ1, AH4, AK4, AH5, AH6, AH2, AH3, AH7, AJ7, AH11, AH12, AH8, AH9, AK10, AH10, AJ13, AH13 4-19 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Power Supply and NC (Cont.) Signal GND1 672 fpBGA A13, A19, A2, A25, AA2, AA25, AB18, AB22, AB5, AB9, AE1, AE11, AE16, AE22, AE26, AE6, AF13, AF19, AF2, AF25, B1, B11, B16, B22, B26, B6, E18, E22, E5, E9, F2, F25, G11, G16, J22, J5, K11, K13, K14, K16, L10, L11, L16, L17, L2, L20, L25, L7, M13, M14, N10, N12, N13, N14, N15, N17, P10, P12, P13, P14, P15, P17, R13, R14, T10, T11, T16, T17, T2, T20, T25, T7, U11, U13, U14, U16, V22, V5, Y11, Y16 900 fpBGA LFE2M50: A1, A13, A18, A24, A30, A7, AA14, AA15, AA16, AA17, AA24, AA27, AA4, AB24, AB7, AD12, AD19, AD27, AE22, AE27, AE4, AE9, AF14, AF17, AF25, AF6, AJ10, AJ21, AJ27, AJ4, AK1, AK13, AK18, AK24, AK30, AK7, B10, B21, B27, B4, D25, D6, E14, E17, F22, F27, F4, F9, G12, G19, J24, J7, K14, K15, K16, K17, K27, K4, L14, L15, L16, L17, M23, M8, N14, N15, N16, N17, N27, N4, P11, P13, P14, P15, P16, P17, P18, P20, R10, R11, R13, R14, R15, R16, R17, R18, R20, R21, R24, R7, T10, T11, T13, T14, T15, T16, T17, T18, T20, T21, T24, T7, U11, U13, U14, U15, U16, U17, U18, U20, V14, V15, V16, V17, V27, V4, W23, W8, Y14, Y15, Y16, Y17 LFE2M70/LFE2M100: A1, A13, A18, A24, A30, A7, AA14, AA15, AA16, AA17, AA24, AA27, AA4, AB24, AB7, AD12, AD19, AD27, AE22, AE27, AE4, AE9, AF14, AF17, AF25, AF6, AJ10, AJ21, AJ27, AJ4, AK1, AK13, AK18, AK24, AK30, AK7, B10, B21, B27, B4, D25, D6, E14, E17, F22, F27, F4, F9, G12, G19, J24, J7, K14, K15, K16, K17, K27, K4, L14, L15, L16, L17, M23, M8, N15, N16, N17, N27, N4, P11, P13, P14, P15, P16, P17, P18, P20, R10, R11, R13, R14, R15, R16, R17, R18, R20, R21, R24, R7, T10, T11, T13, T14, T15, T16, T17, T18, T20, T21, T24, T7, U11, U13, U14, U15, U16, U17, U18, U20, V14, V15, V16, V17, V27, V4, W23, W8, Y14, Y15, Y16, Y17 NC2 LFE2M35: AB3, AB4, AC1, AC2, AD15, AD18, AD20, AD23, AE13, AE25, AF16, AF22, B4, B5, C26, D20, D21, D22, D23, D24, D25, D26, E20, E21, E25, E26, F20, G20, K10, K17, R4, U10, U23, V10, W7, N7, V7 LFE2M50: G5, G4, K7, K8, E1, F2, F1, G3, G2, G1, L9, L7, K6, K5, L8, L6, AA1, AA2, Y3, AB1, Y9, Y8, Y7, AA7, AB2, AB3, AA5, AA6, AB4, AB5, AA8, AA9, AJ1, AK4, AH6, AH3, AH11, AH8, AK10, AJ13, AB26, AB27, Y24, Y25, AA29, Y28, Y30, Y29, W22, LFE2M50: AB3, AB4, AC1, AC2, B4, B5, C26, D20, V22, Y27, Y26, W30, W29, W25, W26, L24, L23, D30, D21, D22, D23, D24, D25, D26, E20, E21, E25, E26, D29, K24, K25, J27, K26, J26, H26, H27, G26, H23, F20, G20, K10, K17, R4, U10, U23, V10, W7, AB21, H24, D28, E28, J18, J19, H17, J17, F18, F17, B13, AC20, AC21, AC22, AC23, AC25, AD26, W20 A10, C8, C11, C3, C6, A4, B1, AA26, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AB19, AB20, AB21, AC11, AC21, AC22, AD21, AD22, AE23, AF20, AF23, AG23, AG26, F20, F23, G10, G20, G21, H19, H20, H21, H22, J20, J21, R9, U22, W9 LFE2M70/LFE2M100: AA26, AB10, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AB19, AB20, AB21, AB9, AC10, AC11, AC21, AC22, AC8, AC9, AD21, AD22, AD4, AD5, AD6, AD7, AD8, AE23, AE5, AE6, AE7, AF20, AF23, AF5, AG23, AG26, D10, E10, E11, F10, F20, F23, F8, G10, G20, G21, G7, G8, G9, H19, H20, H21, H22, H6, H8, H9, J10, J20, J21, J9, K9, R9, U22, W9 1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 2. NC pins should not be connected to any active signals, VCC or GND. 3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks. Specifically, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices using the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details. 4-20 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LatticeECP2M Power Supply and NC (Cont.) Signal VCC VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCJ VCCAUX VCCPLL SERDES Power3 1152 fpBGA AA13, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AB14, AB15, AB20, AB21, N14, N15, N20, N21, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, R13, R14, R21, R22, T14, T21, U14, U21, V14, V21, W14, W21, Y13, Y14, Y21, Y22 C12, C16, E14, H12, H16, M14, M15 C19, C23, E21, H19, H23, M20, M21 G32, K28, K32, N27, N32, P23, R23, T27, T32 AA23, AB27, AB32, AE28, AE32, AH32, W27, W32, Y23 AC20, AC21, AG19, AG23, AK21, AM19, AM23 AC14, AC15, AG12, AG16, AK14, AM12, AM16 AA12, AB3, AB8, AE3, AE7, AH3, W3, W8, Y12 G3, K3, K7, N3, N8, P12, R12, T3, T8 AD28, AG32 AK3 AB12, AB13, AB22, AB23, AC13, AC22, M13, M22, N12, N13, N22, N23 R15, R20, Y15, Y20 D7, B9, B8, D9, B7, E7, B6, D8, E6, D6, D4, B5, D3, B4, C1, B3, B1, B2, B33, B34, B32, C34, B31, D32, B30, D31, E29, D29, D27, B29, E28, B28, D26, B27, B26, D28, AL28, AN26, AN27, AL26, AN28, AK28, AN29, AL27, AL29, AK29, AL31, AN30, AL32, AN31, AM34, AN32, AN34, AN33, AN2, AN1, AN3, AM1, AN4, AL3, AN5, AL4, AL6, AK6, AL8, AN6, AK7, AN7, AL9, AN8, AN9, AL7 A1, A10, A13, A22, A25, A34, AB16, AB17, AB18, AB19, AB26, AB31, AB4, AB9, AC16, AC17, AC18, AC19, AD27, AE27, AE31, AE4, AE8, AF12, AF16, AF19, AF23, AG31, AH31, AH4, AJ14, AJ21, AK27, AK8, AL10, AL16, AL19, AL2, AL25, AL33, AP1, AP10, AP13, AP22, AP25, AP34, D10, D16, D19, D2, D25, D33, E27, E8, F14, F21, G31, G4, J12, J16, J19, J23, K27, K31, K4, K8, M16, M17, M18, M19, N16, N17, N18, N19, N26, N31, N4, N9, R16, R17, R18, R19, T12, T13, T15, T16, T17, T18, T19, T20, T22, T23, T26, T31, T4, T9, U12, U13, U15, U16, U17, U18, U19, U20, U22, U23, V12, V13, V15, V16, V17, V18, V19, V20, V22, V23, W12, W13, W15, W16, W17, W18, W19, W20, W22, W23, W26, W31, W4, W9, Y16, Y17, Y18, Y19 LFE2M70: H2, H1, G5, G6, M9, M10, H3, H4, P3, P4, P9, M7, P1, P2, N7, P7, AC7, AC5, AC6, AD5, AD4, AD3, AD10, AD8, AD2, AD1, AD9, AC11, AD6, AD7, AE1, AE2, AJ12, AH12, AL13, AK13, AE14, AG13, AH22, AH21, AG22, AG21, AF33, AF34, AC27, AC28, AD29, AD30, AE33, AE34, AD32, AD31, AB25, AC25, AB28, AA26, AD33, AD34, P30, P29, P31, P32, R25, T24, N34, N33, F24, G23, J22, G22, H21, K21, L19, L20, L18, K19, J14, L15, H14, K14, F12, D11, F11, E11, A11, A12, A23, A24, AA11, AB11, AC26, AC30, AD11, AD12, AD13, AD14, AD15, AD19, AD21, AD22, AD23, AE10, AE11, AE12, AE13, AE19, AE21, AE22, AE23, AF11, AF21, AF22, AF24, AF8, AF9, AG10, AG11, AG24, AG25, AG26, AG3, AG7, AG8, AG9, AH10, AH11, AH13, AH24, AH25, AH26, AH27, AH5, AH6, AH7, AH8, AH9, AJ10, AJ11, AJ13, AJ24, AJ25, AJ26, AJ27, AJ3, AJ4, AJ5, AJ6, AJ7, AJ8, AJ9, AK10, AK11, AK12, AK24, AK25, AK26, AK4, AK9, AL11, AL12, AL34, AM10, AM11, AM13, AM25, AN10, AN11, AN12, AN13, AN24, AN25, AP11, AP12, AP24, B10, B11, B12, B13, B22, B23, B24, B25, C10, C11, C13, C22, C24, C25, D1, D15, D24, D34, E10, E24, E25, E26, E3, E31, E32, E33, E34, E4, E9, F10, F25, F26, F27, F28, F29, F30, F31, F32, F33, F34, F5, F6, F7, F8, F9, G10, G11, G24, G25, G26, G27, G28, G29, G30, G33, G34, G7, G8, G9, H10, H11, H24, H25, H26, H27, H28, H29, H8, H9, J10, J11, J24, J25, J26, J9, K10, K11, K12, K13, K23, K24, K25, K26, L11, L12, L13, L14, L21, L22, L23, L24, L25, L26, M11, M24, M25, M6, M8, N10, N11, P10, P25, P26, R9, T11, U11, W11, Y10, Y11 LFE2M100: A11, A12, A23, A24, AA11, AB11, AC26, AC30, AD11, AD12, AD13, AD14, AD15, AD19, AD21, AD22, AD23, AE10, AE11, AE12, AE13, AE19, AE21, AE22, AE23, AF11, AF21, AF22, AF24, AF8, AF9, AG10, AG11, AG24, AG25, AG26, AG3, AG7, AG8, AG9, AH10, AH11, AH13, AH24, AH25, AH26, AH27, AH5, AH6, AH7, AH8, AH9, AJ10, AJ11, AJ13, AJ24, AJ25, AJ26, AJ27, AJ3, AJ4, AJ5, AJ6, AJ7, AJ8, AJ9, AK10, AK11, AK12, AK24, AK25, AK26, AK4, AK9, AL11, AL12, AL34, AM10, AM11, AM13, AM25, AN10, AN11, AN12, AN13, AN24, AN25, AP11, AP12, AP24, B10, B11, B12, B13, B22, B23, B24, B25, C10, C11, C13, C22, C24, C25, D1, D15, D24, D34, E10, E24, E25, E26, E3, E31, E32, E33, E34, E4, E9, F10, F25, F26, F27, F28, F29, F30, F31, F32, F33, F34, F5, F6, F7, F8, F9, G10, G11,G24, G25, G26, G27, G28, G29, G30, G33, G34, G7, G8, G9, H10, H11, H24, H25, H26, H27, H28, H29, H8, H9, J10, J11, J24, J25, J26, J9, K10, K11, K12, K13, K23, K24, K25, K26, L11, L12, L13, L14, L21, L22, L23, L24, L25, L26, M11, M24, M25, M6, M8, N10, N11, P10, P25, P26, R9, T11, U11, W11, Y10, Y11 GND1 NC2 1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 2. NC pins should not be connected to any active signals, VCC or GND. 3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks. Specifically, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices using the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details. 4-21 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP LFE2-6E/SE Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 LFE2-12E/12SE Differential T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C Pin/Pad Function PL2A PL2B PL4A PL4B PL6A VCCAUX PL6B PL8A VCCIO7 PL8B GND PL12A PL12B PL13A PL13B VCC PL15A PL15B PL16A PL16B GND VCC PL18A PL18B LLM0_PLLCAP PL20A PL20B PL22A VCC GND VCCIO6 TCK TDI TDO VCCJ TMS PB2A PB2B VCCAUX PB4A PB4B VCCIO5 PB6A PB6B NC Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 Dual Function VREF2_7 VREF1_7 Pin/Pad Function PL2A PL2B PL4A PL4B PL6A VCCAUX PL6B PL8A VCCIO7 PL8B GND PL12A PL12B PL13A PL13B VCC PL15A PL15B PL16A PL16B GND VCC Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 PCLKT7_0/LDQ10 PCLKC7_0/LDQ10 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C PCLKT7_0/LDQ10 PCLKC7_0/LDQ10 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A LLM0_GPLLT_IN_A** LLM0_GPLLC_IN_A** T C T (LVDS)* C (LVDS)* PL18A PL18B LLM0_PLLCAP PL20A PL20B PL22A VCC GND VCCIO6 TCK TDI TDO VCCJ TMS LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A LLM0_GPLLT_IN_A** LLM0_GPLLC_IN_A** T C T (LVDS)* C (LVDS)* VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQS6 BDQ6 T C T C T C PB2A PB2B VCCAUX PB6A PB6B VCCIO5 PB12A PB12B PB16A VREF2_5/BDQ6 VREF1_5/BDQ6 BDQS6 BDQ6 BDQ15 BDQ15 BDQ15 T C T C T C T 4-22 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 LFE2-12E/12SE Differential Pin/Pad Function PB16B GND VCC Pin/Pad Function NC GND VCC PB8A PB8B GND PB13A PB13B VCC PB14A PB14B PB16A PB16B PB18A PB18B GND PB20A PB20B VCCIO4 PB22A PB22B PB24A PB24B PB26A PB26B PB28A PB28B CFG1 CFG2 PROGRAMN INITN CFG0 CCLK DONE PR29A GND PR26A VCC PR25B VCCIO8 PR25A PR24B PR24A VCCIO3 VCCAUX Bank 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 - Dual Function Bank 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 - Dual Function BDQ15 Differential C PCLKT5_0/BDQ6 PCLKC5_0/BDQ6 PCLKT4_0/BDQ15 PCLKC4_0/BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ24 BDQ24 BDQ24 BDQ24 BDQS24 BDQ24 BDQ24 BDQ24 VREF2_4/BDQ24 VREF1_4/BDQ24 T C T C T C T C T C T C T C T C T C T C PB26A PB26B GND PB31A PB31B VCC PB34A PB34B PB40A PB40B PB44A PB44B GND PB48A PB48B VCCIO4 PB50A PB50B PB52A PB52B PB54A PB54B PB55A PB55B CFG1 CFG2 PROGRAMN INITN CFG0 CCLK DONE PCLKT5_0/BDQ24 PCLKC5_0/BDQ24 PCLKT4_0/BDQ33 PCLKC4_0/BDQ33 BDQ33 BDQ33 BDQ42 BDQ42 BDQ42 BDQ42 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 VREF2_4/BDQ51 VREF1_4/BDQ51 T C T C T C T C T C T C T C T C T C T C D0/SPIFASTN D6 D7 DI/CSSPI0N DOUT/CSON BUSY/SISPI C T C T PR29A GND PR26A VCC PR25B VCCIO8 PR25A PR24B PR24A VCCIO3 VCCAUX D0/SPIFASTN D6 D7 DI/CSSPI0N DOUT/CSON BUSY/SISPI C T C T 4-23 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Number 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 LFE2-12E/12SE Differential C (LVDS)* T (LVDS)* Pin/Pad Function PR20B PR20A RLM0_PLLCAP VCC GND PR17B PR17A PR16B PR16A PR15B PR15A VCC PR13B PR13A GND VCCIO2 PR2B PR2A PT28B PT28A PT26B PT26A PT24B PT24A PT22B PT22A VCCIO1 PT20B PT20A GND PT18B PT18A PT16A NC PT14B PT14A NC VCC PT12B PT12A PT10B XRES GND PT10A VCC Bank 3 3 3 3 3 3 3 3 3 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 - Dual Function RLM0_GPLLC_IN_A** RLM0_GPLLT_IN_A** Pin/Pad Function PR20B PR20A RLM0_PLLCAP VCC GND Bank 3 3 3 3 3 3 3 3 3 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 - Dual Function RLM0_GPLLC_IN_A** RLM0_GPLLT_IN_A** Differential C (LVDS)* T (LVDS)* RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ10 PCLKT2_0/RDQ10 C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T PR17B PR17A PR16B PR16A PR15B PR15A VCC PR13B PR13A GND VCCIO2 RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ10 PCLKT2_0/RDQ10 C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T VREF2_2 VREF1_2 VREF2_1 VREF1_1 C (LVDS)* T (LVDS)* C T C T C T C T C T C T PR2B PR2A PT55B PT55A PT54B PT54A PT52B PT52A PT50B PT50A VCCIO1 PT48B PT48A GND PT44B PT44A PT40B PT40A VREF2_2 VREF1_2 VREF2_1 VREF1_1 C (LVDS)* T (LVDS)* C T C T C T C T C T C T C T C T C T PT34B PT34A NC VCC PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C PT30B PT30A PT28B XRES GND PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C PCLKT0_0 T PT28A VCC PCLKT0_0 T 4-24 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.) LFE2-6E/SE Pin Number 136 137 138 139 140 141 142 143 144 LFE2-12E/12SE Differential C T Pin/Pad Function PT6B PT6A GND VCCIO0 PT4B PT4A VCCAUX PT2B PT2A Bank 0 0 0 0 0 0 0 Dual Function Pin/Pad Function PT16B PT16A GND VCCIO0 Bank 0 0 0 0 0 0 0 Dual Function Differential C T C T VREF2_0 VREF1_0 C T PT6B PT6A VCCAUX PT2B PT2A C T VREF2_0 VREF1_0 C T * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one connection with a package ball or pin. 4-25 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP LFE2-12E/SE Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin/Pad Function PL2A PL2B PL4A PL4B GND PL6A VCCAUX PL6B PL8A VCCIO7 PL8B VCC GND VCCIO7 PL12A PL12B GND PL13A VCC PL13B PL15A PL15B PL16A PL16B GND PL17A PL17B VCC LLM0_PLLCAP VCCAUX PL20A GND PL21A PL20B PL21B PL23A PL24A VCCIO6 PL24B VCC PL26A GND PL26B VCCIO6 PL28A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQS28 T (LVDS)* LDQ28 C (LVDS)* LDQ28 T (LVDS)* LDQ28 C (LVDS)* LDQ28 T (LVDS)* LLM0_GPLLT_FB_A LLM0_GPLLC_IN_A** LLM0_GPLLC_FB_A T C (LVDS)* C LLM0_GPLLT_IN_A** T (LVDS)* LLM0_GDLLT_IN_A** LLM0_GDLLC_IN_A** T (LVDS)* C (LVDS)* PCLKC7_0/LDQ10 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T (LVDS)* C (LVDS)* T C PCLKT7_0/LDQ10 T LDQ10 LDQ10 T (LVDS)* C (LVDS)* LDQ10 C (LVDS)* LDQ10 LDQ10 C (LVDS)* T (LVDS)* LDQ10 T (LVDS)* Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* Pin/Pad Function PL2A PL2B PL6A PL6B GND PL12A VCCAUX PL12B PL14A VCCIO7 PL14B VCC GND VCCIO7 PL18A PL18B GND PL19A VCC PL19B PL21A PL21B PL22A PL22B GND PL27A PL27B VCC LLM0_PLLCAP VCCAUX PL30A GND PL31A PL30B PL31B PL33A PL38A VCCIO6 PL38B VCC PL40A GND PL40B VCCIO6 PL42A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQS42 T (LVDS)* LDQ42 C (LVDS)* LDQ42 T (LVDS)* LDQ42 C (LVDS)* LLM0_GPLLT_FB_A/LDQ34 LLM0_GPLLC_IN_A**/LDQ34 LLM0_GPLLC_FB_A/LDQ34 LDQ34 LDQ42 T (LVDS)* T C (LVDS)* C LLM0_GPLLT_IN_A**/LDQ34 T (LVDS)* LLM0_GDLLT_IN_A**/LDQ25 LLM0_GDLLC_IN_A**/LDQ25 T (LVDS)* C (LVDS)* PCLKC7_0/LDQ16 PCLKT6_0/LDQ25 PCLKC6_0/LDQ25 VREF2_6/LDQ25 VREF1_6/LDQ25 C T (LVDS)* C (LVDS)* T C PCLKT7_0/LDQ16 T LDQ16 LDQ16 T (LVDS)* C (LVDS)* LDQ16 C (LVDS)* LDQ16 LDQ16 C (LVDS)* T (LVDS)* LDQ16 T (LVDS)* LFE2-20E/SE Dual Function VREF2_7 VREF1_7 LDQ8 LDQ8 Differential T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* 4-26 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Pin/Pad Function PL28B PL30A TCK TDI TDO VCCJ TMS PB2A PB2B VCCIO5 PB6A PB6B PB8A PB8B GND PB12A PB12B VCCIO5 PB16A PB16B PB18A PB18B GND PB20A VCCAUX PB20B PB22A PB22B VCC PB26A PB26B GND PB31A PB31B VCC GND PB34A PB34B PB36A PB36B VCCAUX PB40A PB40B GND PB42A PB42B Bank 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 BDQS42 BDQ42 T C BDQ42 BDQ42 T C BDQ33 BDQ33 BDQ33 BDQ33 T C T C PCLKT4_0/BDQ33 PCLKC4_0/BDQ33 T C PCLKT5_0/BDQ24 PCLKC5_0/BDQ24 T C BDQ24 BDQ24 BDQ24 C T C BDQ24 T BDQ15 BDQ15 BDQ15 BDQ15 T C T C BDQ15 BDQ15 T C BDQS6 BDQ6 BDQ6 BDQ6 T C T C VREF2_5/BDQ6 VREF1_5/BDQ6 T C Dual Function LDQ28 LDQ28 Differential C (LVDS)* Pin/Pad Function PL42B PL44A TCK TDI TDO VCCJ TMS PB2A PB2B VCCIO5 PB6A PB6B PB8A PB8B GND PB12A PB12B VCCIO5 PB16A PB16B PB18A PB18B GND PB30A VCCAUX PB30B PB32A PB32B VCC PB35A PB35B GND PB40A PB40B VCC GND PB42A PB42B PB44A PB44B VCCAUX PB50A PB50B GND PB52A PB52B Bank 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 BDQ51 BDQ51 T C BDQ51 BDQ51 T C BDQS42 BDQ42 BDQ42 BDQ42 T C T C PCLKT4_0/BDQ42 PCLKC4_0/BDQ42 T C PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 T C BDQ33 BDQ33 BDQ33 C T C BDQ33 T BDQ15 BDQ15 BDQ15 BDQ15 T C T C BDQ15 BDQ15 T C BDQS6 BDQ6 BDQ6 BDQ6 T C T C VREF2_5/BDQ6 VREF1_5/BDQ6 T C LFE2-20E/SE Dual Function LDQ42 LDQ42 Differential C (LVDS)* 4-27 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Number 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 Pin/Pad Function PB44A VCCIO4 PB44B PB48A PB48B VCC PB52A PB52B VCCIO4 PB54A GND PB55A PB55B CFG1 PROGRAMN CFG2 INITN CFG0 CCLK DONE PR29A VCCIO8 PR26A GND VCC PR25B VCCIO8 PR25A PR24B PR24A GND VCCIO3 PR21A VCCAUX PR20B PR20A RLM0_PLLCAP VCC PR18B PR18A PR17B PR17A PR16B VCCIO3 PR16A PR15B Bank 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF1_3 PCLKC3_0 T C (LVDS)* RLM0_GDLLC_FB_A RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** VREF2_3 C T C (LVDS)* T (LVDS)* C RLM0_GPLLC_IN_A** RLM0_GPLLT_IN_A** C (LVDS)* T (LVDS)* RLM0_GPLLT_FB_A DI/CSSPI0N DOUT/CSON BUSY/SISPI T C T D7 C D6 D0/SPIFASTN VREF2_4/BDQ51 VREF1_4/BDQ51 T C BDQ51 BDQ51 BDQ51 T C BDQ42 BDQ51 BDQ51 C T C Dual Function BDQ42 Differential T Pin/Pad Function PB54A VCCIO4 PB54B PB58A PB58B VCC PB60A PB60B VCCIO4 PB63A GND PB64A PB64B CFG1 PROGRAMN CFG2 INITN CFG0 CCLK DONE PR43A VCCIO8 PR40A GND VCC PR39B VCCIO8 PR39A PR38B PR38A GND VCCIO3 PR31A VCCAUX PR30B PR30A RLM0_PLLCAP VCC PR28B PR28A PR27B PR27A PR22B VCCIO3 PR22A PR21B Bank 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF1_3/RDQ25 PCLKC3_0/RDQ25 T C (LVDS)* RLM0_GDLLC_FB_A/RDQ25 RLM0_GDLLT_FB_A**/RDQ25 RLM0_GDLLC_IN_A/RDQ25 RLM0_GDLLT_IN_A**/RDQ25 VREF2_3/RDQ25 C T C (LVDS)* T (LVDS)* C RLM0_GPLLC_IN_A**/RDQ34 RLM0_GPLLT_IN_A**/RDQ34 C (LVDS)* T (LVDS)* RLM0_GPLLT_FB_A/RDQ34 DI/CSSPI0N DOUT/CSON BUSY/SISPI T C T D7 C D6 D0/SPIFASTN VREF2_4/BDQ60 VREF1_4/BDQ60 T C BDQ60 BDQS60 BDQ60 T C BDQ51 BDQ60 BDQ60 C T C LFE2-20E/SE Dual Function BDQ51 Differential T 4-28 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Number 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 Pin/Pad Function PR15A GND VCC PR13B PR13A VCCIO2 PR12A GND VCC PR8B VCCIO2 PR8A PR6B VCCAUX PR6A PR4B PR4A PR2B PR2A PT55B PT55A GND PT54B PT54A VCCIO1 PT52B PT52A PT50B PT50A PT48B PT48A GND VCCIO1 VCC PT40B PT40A VCCAUX GND PT36B PT36A PT34B PT34A PT30B PT30A XRES PT28B Bank 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T C T C T C T C T C T C T C T VREF2_2 VREF1_2 VREF2_1 VREF1_1 RDQ10 T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* T (LVDS)* C T RDQ10 RDQ10 T (LVDS)* C (LVDS)* RDQ10 C (LVDS)* RDQ10 PCLKC2_0/RDQ10 PCLKT2_0/RDQ10 C T Dual Function PCLKT3_0 Differential T (LVDS)* Pin/Pad Function PR21A GND VCC PR19B PR19A VCCIO2 PR16A GND VCC PR14B VCCIO2 PR14A PR12B VCCAUX PR12A PR6B PR6A PR2B PR2A PT64B PT64A GND PT62B PT62A VCCIO1 PT60B PT60A PT58B PT58A PT56B PT56A GND VCCIO1 VCC PT50B PT50A VCCAUX GND PT44B PT44A PT42B PT42A PT39B PT39A XRES PT37B Bank 3 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T C T C T C T C T C T C T C T RDQ16 RDQ8 RDQ8 VREF2_2 VREF1_2 VREF2_1 VREF1_1 T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* T (LVDS)* C T RDQ16 RDQ16 T (LVDS)* C (LVDS)* RDQ16 C (LVDS)* RDQS16 PCLKC2_0/RDQ16 PCLKT2_0/RDQ16 C T LFE2-20E/SE Dual Function PCLKT3_0/RDQ25 Differential T (LVDS)* 4-29 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP (Cont.) LFE2-12E/SE Pin Number 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin/Pad Function GND PT28A PT26B PT26A VCC PT20B VCCAUX PT20A GND PT18B PT18A VCCIO0 PT16B PT16A VCC PT12B PT12A GND PT8B PT8A PT6B PT6A VCCIO0 PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 C T C T C T C T C T C T T C PCLKT0_0 T C T Dual Function Differential Pin/Pad Function GND PT37A PT36B PT36A VCC PT30B VCCAUX PT30A GND PT26B PT26A VCCIO0 PT20B PT20A VCC PT12B PT12A GND PT8B PT8A PT6B PT6A VCCIO0 PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 C T C T C T C T C T C T T C PCLKT0_0 T C T LFE2-20E/SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-30 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA LFE2-6E/SE Ball Number C3 C2 VCCIO D3 D4 D2 GND E4 B1 C1 F5 VCCIO F4 G6 G4 D1 GND E1 F3 G3 VCCIO F2 F1 GND G2 G1 H6 VCCIO H5 H4 GND H3 H2 H1 G10 J4 J5 J6 K4 GND J1 K3 VCCIO J2 LFE2-12E/SE Differential T (LVDS)* C (LVDS)* Ball/Pad Function PL2A PL2B VCCIO7 PL5A PL4A PL5B GNDIO7 PL4B PL7A PL7B PL9A VCCIO7 PL8A PL9B PL8B PL10A GNDIO7 PL10B PL11A PL11B VCCIO7 PL12A PL12B GNDIO7 PL13A PL13B PL15A VCCIO6 PL15B PL16A GNDIO6 PL16B PL17A PL17B VCC PL18A PL18B LLM0_PLLCAP PL20A GNDIO6 PL21A PL20B VCCIO6 PL21B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Dual Function VREF2_7 VREF1_7 Ball/Pad Function PL2A PL2B VCCIO7 - Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* T T (LVDS)* C C (LVDS)* LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 LDQS10 LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 PCLKT7_0/LDQ10 PCLKC7_0/LDQ10 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 LLM0_GDLLT_IN_A** LLM0_GDLLC_IN_A** LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A LLM0_GPLLT_IN_A** LLM0_GPLLT_FB_A LLM0_GPLLC_IN_A** LLM0_GPLLC_FB_A T C T T (LVDS)* C C (LVDS)* T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* T C (LVDS)* C PL5A PL4A PL5B GNDIO7 PL4B PL7A PL7B PL9A VCCIO7 PL8A PL9B PL8B PL10A GNDIO7 PL10B PL11A PL11B VCCIO7 PL12A PL12B GNDIO7 PL13A PL13B PL15A VCCIO6 PL15B PL16A GNDIO6 PL16B PL17A PL17B VCC PL18A PL18B LLM0_PLLCAP PL20A GNDIO6 PL21A PL20B VCCIO6 PL21B T T (LVDS)* C C (LVDS)* LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 LDQS10 LDQ10 LDQ10 LDQ10 LDQ10 LDQ10 PCLKT7_0/LDQ10 PCLKC7_0/LDQ10 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 LLM0_GDLLT_IN_A** LLM0_GDLLC_IN_A** LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A LLM0_GPLLT_IN_A** LLM0_GPLLT_FB_A LLM0_GPLLC_IN_A** LLM0_GPLLC_FB_A T C T T (LVDS)* C C (LVDS)* T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* T C (LVDS)* C 4-31 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Number GND L2 K2 L3 K1 VCCIO L4 L1 L5 M1 GND N1 N2 P1 VCCIO P2 R1 GND R2 N4 M4 P3 N3 K7 M5 K6 M6 R3 P4 N5 N6 T2 P6 VCCIO T3 R6 GND R4 L6 T4 L7 N7 VCCIO LFE2-12E/SE Differential T (LVDS)* T C (LVDS)* C T (LVDS)* T C (LVDS)* C T T (LVDS)* C C (LVDS)* T (LVDS)* C (LVDS)* Ball/Pad Function GNDIO6 PL24A PL25A PL24B PL25B VCCIO6 PL26A PL27A PL26B PL27B GNDIO6 PL29A PL28A PL29B VCCIO6 PL28B PL30A GNDIO6 PL30B TDI TCK TDO TMS VCCJ PB2A NC PB2B NC NC PB3A PB3B PB4A PB5A VCCIO5 PB4B PB5B GNDIO5 PB6A PB7A PB6B PB7B PB8A VCCIO5 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dual Function LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQS28 LDQ28 LDQ28 LDQ28 LDQ28 Ball/Pad Function GNDIO6 PL24A PL25A PL24B PL25B VCCIO6 PL26A PL27A PL26B PL27B GNDIO6 PL29A PL28A PL29B VCCIO6 PL28B PL30A GNDIO6 PL30B TDI TCK TDO TMS VCCJ Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dual Function LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQ28 LDQS28 LDQ28 LDQ28 LDQ28 LDQ28 Differential T (LVDS)* T C (LVDS)* C T (LVDS)* T C (LVDS)* C T T (LVDS)* C C (LVDS)* T (LVDS)* C (LVDS)* VREF2_5/BDQ6 VREF1_5/BDQ6 T C PB2A PB3A PB2B PB5A PB5B VCCIO GNDIO5 VREF2_5/BDQ6 BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 T C T C BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 BDQS6 BDQ6 BDQ6 BDQ6 PCLKT5_0/BDQ6 T C T T C C T T C C T PB21A PB21B PB22A PB23A VCCIO5 PB22B PB23B GNDIO5 PB24A PB25A PB24B PB25B PB26A VCCIO5 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQS24 BDQ24 BDQ24 BDQ24 PCLKT5_0/BDQ24 T C T T C C T T C C T 4-32 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Number M8 GND P7 R8 VCCIO T5 T6 T8 GND R7 T9 T7 L8 VCCIO P8 L9 N8 R9 GND R10 N9 T10 M9 R11 P10 N11 VCCIO N10 P11 T11 GND M11 T12 L11 T13 R13 VCCIO T14 P13 GND N12 M12 R15 LFE2-12E/SE Differential C T C T C T T C C T T C C T C Ball/Pad Function PB8B GNDIO5 PB13A PB13B VCCIO4 PB14A PB14B PB15A GNDIO4 PB16A PB15B PB16B PB17A VCCIO4 PB18A PB17B PB18B PB19A GNDIO4 PB19B PB20A PB21A PB20B PB21B PB22A PB23A VCCIO4 PB22B PB23B PB24A GNDIO4 PB25A PB24B PB25B PB26A PB27A VCCIO4 PB26B PB27B GNDIO4 PB28A PB28B CFG2 Bank 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 Dual Function PCLKC5_0/BDQ6 PCLKT4_0/BDQ15 PCLKC4_0/BDQ15 BDQ15 BDQ15 BDQS15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 Ball/Pad Function PB26B GNDIO5 PB31A PB31B VCCIO4 PB32A PB32B PB33A GNDIO4 PB34A PB33B PB34B PB35A VCCIO4 PB36A PB35B PB36B PB37A GNDIO4 PB37B VCCIO GNDIO4 Bank 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 Dual Function PCLKC5_0/BDQ24 PCLKT4_0/BDQ33 PCLKC4_0/BDQ33 BDQ33 BDQ33 BDQS33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 Differential C T C T C T T C C T T C C T C BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQS24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 VREF2_4/BDQ24 VREF1_4/BDQ24 T T C C T T C C T T C C T T C C T C PB47A PB48A PB47B PB48B PB49A PB50A VCCIO4 PB49B PB50B PB51A GNDIO4 PB52A PB51B PB52B PB53A PB54A VCCIO4 PB53B PB54B GNDIO4 PB55A PB55B CFG2 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 VREF2_4/BDQ51 VREF1_4/BDQ51 T T C C T T C C T T C C T T C C T C 4-33 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Number N14 N13 N15 P15 L12 N16 GND R14 P14 M13 R16 VCCIO M16 P16 L15 GND L14 L16 L10 L13 VCCIO K11 K14 K13 GND K15 VCCIO K16 GND J16 J15 J14 J13 J12 H12 GND H13 H15 VCCIO H16 H11 J11 G16 GND G15 LFE2-12E/SE Differential Ball/Pad Function CFG1 PROGRAMN CFG0 Ball/Pad Function CFG1 PROGRAMN CFG0 PR30B INITN PR29B GNDIO8 CCLK PR30A DONE PR28B VCCIO8 PR29A PR28A PR27B GNDIO8 PR26A PR27A PR25B PR26B VCCIO8 PR25A PR24B PR24A GNDIO8 PR21B VCCIO3 PR21A GNDIO3 PR20B PR20A RLM0_PLLCAP PR18B PR18A PR17B GNDIO3 PR17A PR16B VCCIO3 PR16A PR15B PR15A PR13B GNDIO2 PR13A Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 Dual Function Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 Dual Function Differential WRITEN CSN C C PR30B INITN PR29B GNDIO8 CCLK WRITEN CSN C C CS1N D1 D0/SPIFASTN D2 D3 D6 D4 D7 D5 DI/CSSPI0N DOUT/CSON BUSY/SISPI RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A RLM0_GPLLC_IN_A** RLM0_GPLLT_IN_A** RLM0_GDLLC_FB_A RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ10 PCLKT2_0/RDQ10 T C T T C T T C C T C T C T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T PR30A DONE PR28B VCCIO8 PR29A PR28A PR27B GNDIO8 PR26A PR27A PR25B PR26B VCCIO8 PR25A PR24B PR24A GNDIO8 PR21B VCCIO3 PR21A GNDIO3 PR20B PR20A RLM0_PLLCAP PR18B PR18A PR17B GNDIO3 PR17A PR16B VCCIO3 PR16A PR15B PR15A PR13B GNDIO2 PR13A CS1N D1 D0/SPIFASTN D2 D3 D6 D4 D7 D5 DI/CSSPI0N DOUT/CSON BUSY/SISPI RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A RLM0_GPLLC_IN_A** RLM0_GPLLT_IN_A** RLM0_GDLLC_FB_A RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ10 PCLKT2_0/RDQ10 T C T T C T T C C T C T C T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T 4-34 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Number F15 G11 F14 VCCIO F12 G14 G13 GND F16 F9 E16 F10 VCCIO D16 D15 C15 C16 GND D14 B16 F13 VCCIO E13 F11 E11 GND A15 E12 B15 VCCIO D12 B14 C14 A14 D13 C13 GND A13 B13 VCCIO A12 B11 D11 A11 C11 LFE2-12E/SE Differential C C (LVDS)* T T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* C T (LVDS)* T C T C (LVDS)* C T (LVDS)* T Ball/Pad Function PR11B PR12B PR11A VCCIO2 PR12A PR10B PR10A GNDIO2 PR8B PR9B PR8A PR9A VCCIO2 PR7B PR7A PR4B PR5B GNDIO2 PR4A PR5A PR2B VCCIO2 PR2A PT28B PT28A GNDIO1 PT27B PT26B PT27A VCCIO1 PT26A PT25B PT24B PT25A PT24A PT23B GNDIO1 PT22B PT23A VCCIO1 PT22A PT21B PT20B PT21A PT20A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function RDQ10 RDQ10 RDQ10 RDQ10 RDQ10 RDQS10 RDQ10 RDQ10 RDQ10 RDQ10 RDQ10 RDQ10 Ball/Pad Function PR11B PR12B PR11A VCCIO2 PR12A PR10B PR10A GNDIO2 PR8B PR9B PR8A PR9A VCCIO2 PR7B PR7A PR4B PR5B GNDIO2 PR4A PR5A PR2B VCCIO2 PR2A PT55B PT55A GNDIO1 PT54B PT53B PT54A VCCIO1 PT53A PT52B PT51B PT52A PT51A PT50B GNDIO1 PT49B PT50A VCCIO1 PT49A PT48B PT47B PT48A PT47A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function RDQ10 RDQ10 RDQ10 RDQ10 RDQ10 RDQS10 RDQ10 RDQ10 RDQ10 RDQ10 RDQ10 RDQ10 Differential C C (LVDS)* T T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* C T (LVDS)* T C T C (LVDS)* C T (LVDS)* T VREF2_2 VREF1_2 VREF2_1 VREF1_1 C (LVDS)* T (LVDS)* C T C C T T C C T T C C T T C C T T VREF2_2 VREF1_2 VREF2_1 VREF1_1 C (LVDS)* T (LVDS)* C T C C T T C C T T C C T T C C T T 4-35 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Number D10 C10 GND B10 A9 A10 B9 VCCIO A8 D9 B8 C9 GND B7 E9 A7 D8 VCCIO A6 B6 E6 F8 GND E8 A5 A3 A4 VCCIO B3 A2 C7 B2 D7 D6 GND F7 C6 VCCIO F6 C4 B4 - LFE2-12E/SE Differential Ball/Pad Function GNDIO1 VCCIO C T C C T T C C T T C C T T PT37B PT37A GNDIO1 PT36B PT35B PT36A PT35A VCCIO1 PT34B PT33B PT34A PT33A GNDIO1 PT32B PT31B PT32A PT31A VCCIO1 PT30B PT30A XRES PT28B GNDIO0 PT28A PT27B PT26B PT27A VCCIO0 T C C T T C C T T C T PT26A PT25B PT24B PT25A PT24A PT23B GNDIO0 PT22B PT23A VCCIO0 PT22A PT21B PT21A GNDIO0 VCCIO Ball/Pad Function PT19B PT19A GNDIO1 PT18B PT17B PT18A PT17A VCCIO1 PT16B PT15B PT16A PT15A GNDIO1 PT14B PT13B PT14A PT13A VCCIO1 PT12B PT12A XRES PT10B GNDIO0 PT10A PT9B PT8B PT9A VCCIO0 PT8A PT7B PT6B PT7A PT6A PT5B GNDIO0 PT4B PT5A VCCIO0 PT4A PT3B PT3A - Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - Dual Function Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Dual Function Differential C T C C T T C C T T C C T T PCLKC1_0 PCLKT1_0 PCLKC0_0 PCLKT0_0 C T C T C C T T C C T T C C T T C T PCLKC1_0 PCLKT1_0 PCLKC0_0 PCLKT0_0 C T C T C C T 4-36 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Number D5 E5 G7 G9 H7 J10 K10 K8 G8 H10 J7 K9 C5 E7 C12 E10 E14 G12 K12 M14 M10 P12 M7 P5 K5 M3 E3 G5 T15 A1 A16 B12 B5 C8 E15 E2 H14 H8 H9 J3 J8 J9 M15 M2 P9 LFE2-12E/SE Differential C T Ball/Pad Function PT2B PT2A VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 0 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 - Dual Function VREF2_0 VREF1_0 Ball/Pad Function PT2B PT2A VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 0 0 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 - Dual Function VREF2_0 VREF1_0 Differential C T 4-37 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-6E/SE Ball Number R12 R5 T1 T16 LFE2-12E/SE Differential Ball/Pad Function GND GND GND GND Ball/Pad Function GND GND GND GND Bank - Dual Function Bank - Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-38 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA LFE2-20E/SE Ball Number C3 C2 VCCIO D3 D4 D2 GND E4 B1 C1 F5 VCCIO F4 G6 G4 D1 GND E1 F3 G3 VCCIO F2 F1 GND G2 G1 H6 VCCIO H5 H4 GND H3 H2 H1 G10 J4 J5 J6 K4 GND Ball Number C3 C2 VCCIO GND D3 D4 D2 GND E4 B1 C1 F5 VCC F4 G6 G4 D1 GND E1 F3 G3 VCCIO F2 F1 GND G2 G1 H6 VCCIO H5 H4 GND H3 H2 H1 G10 J4 J5 J6 K4 GND Ball/Pad Function PL2A PL2B VCCIO7 GNDIO7 PL7A PL6A PL7B GNDIO7 PL6B PL13A PL13B PL15A VCCIO PL14A PL15B PL14B PL16A GNDIO7 PL16B PL17A PL17B VCCIO7 PL18A PL18B GNDIO7 PL19A PL19B PL21A VCCIO6 PL21B PL22A GNDIO6 PL22B PL27A PL27B VCC PL28A PL28B LLM0_PLLCAP PL30A GNDIO6 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 - Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* LDQ8 LDQ8 LDQ8 LDQ8 LDQ16 LDQ16 LDQ16 LDQ16 LDQ16 LDQ16 LDQS16 LDQ16 LDQ16 LDQ16 LDQ16 LDQ16 PCLKT7_0/LDQ16 PCLKC7_0/LDQ16 PCLKT6_0/LDQ25 PCLKC6_0/LDQ25 VREF2_6/LDQ25 VREF1_6/LDQ25 LLM0_GDLLT_IN_A**/LDQ25 LLM0_GDLLC_IN_A**/LDQ25 LLM0_GDLLT_FB_A/LDQ25 LLM0_GDLLC_FB_A/LDQ25 LLM0_GPLLT_IN_A**/LDQ34 T T (LVDS)* C C (LVDS)* T C T T (LVDS)* C C (LVDS)* T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C T (LVDS)* 4-39 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number J1 K3 VCCIO J2 GND L2 K2 L3 K1 VCCIO L4 L1 L5 M1 GND N1 N2 P1 VCCIO P2 R1 GND R2 N4 M4 P3 N3 K7 M5 K6 M6 R3 P4 N5 N6 T2 P6 VCCIO T3 R6 Ball Number J1 K3 VCCIO J2 GND L2 K2 L3 K1 VCCIO L4 L1 L5 M1 GND N1 N2 P1 VCCIO P2 R1 GND R2 N4 M4 P3 N3 K7 M5 K6 M6 R3 P4 VCC GND N5 N6 T2 P6 VCCIO T3 R6 Ball/Pad Function PL31A PL30B VCCIO6 PL31B GNDIO6 PL38A PL39A PL38B PL39B VCCIO6 PL40A PL41A PL40B PL41B GNDIO6 PL43A PL42A PL43B VCCIO6 PL42B PL44A GNDIO6 PL44B TDI TCK TDO TMS VCCJ PB2A PB3A PB2B PB5A PB5B VCCIO GNDIO5 PB30A PB30B PB31A PB32A VCCIO5 PB31B PB32B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dual Function LLM0_GPLLT_FB_A/LDQ34 LLM0_GPLLC_IN_A**/LDQ34 LLM0_GPLLC_FB_A/LDQ34 LDQ42 LDQ42 LDQ42 LDQ42 LDQ42 LDQ42 LDQ42 LDQ42 LDQ42 LDQS42 LDQ42 LDQ42 LDQ42 LDQ42 Differential T C (LVDS)* C T (LVDS)* T C (LVDS)* C T (LVDS)* T C (LVDS)* C T T (LVDS)* C C (LVDS)* T (LVDS)* C (LVDS)* VREF2_5/BDQ6 BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 T C T C BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T T C C 4-40 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number GND R4 L6 T4 L7 N7 VCCIO M8 GND P7 R8 VCCIO T5 T6 T8 GND R7 T9 T7 L8 VCCIO P8 L9 N8 R9 GND R10 N9 T10 M9 R11 P10 N11 VCCIO N10 P11 T11 GND M11 T12 Ball Number GND R4 L6 T4 L7 N7 VCCIO M8 GND P7 R8 VCCIO T5 T6 T8 GND R7 T9 T7 L8 VCCIO P8 L9 N8 R9 GND R10 VCC GND N9 T10 M9 R11 P10 N11 VCCIO N10 P11 T11 GND M11 T12 Ball/Pad Function GNDIO5 PB33A PB34A PB33B PB34B PB35A VCCIO5 PB35B GNDIO5 PB40A PB40B VCCIO4 PB41A PB41B PB42A GNDIO4 PB43A PB42B PB43B PB44A VCCIO4 PB45A PB44B PB45B PB46A GNDIO4 PB46B VCCIO GNDIO4 PB56A PB57A PB56B PB57B PB58A PB59A VCCIO4 PB58B PB59B PB60A GNDIO4 PB61A PB60B Bank 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Dual Function BDQS33 BDQ33 BDQ33 BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 PCLKT4_0/BDQ42 PCLKC4_0/BDQ42 BDQ42 BDQ42 BDQS42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 Differential T T C C T C T C T C T T C C T T C C T C BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQS60 BDQ60 BDQ60 T T C C T T C C T T C 4-41 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number L11 T13 R13 VCCIO T14 P13 GND N12 M12 R15 N14 N13 N15 P15 L12 N16 GND R14 P14 M13 R16 VCCIO M16 P16 L15 GND L14 L16 L10 L13 VCCIO K11 K14 K13 GND K15 VCCIO K16 GND J16 J15 J14 Ball Number L11 T13 R13 VCCIO T14 P13 GND N12 M12 R15 N14 N13 N15 P15 L12 N16 GND R14 P14 M13 R16 VCCIO M16 P16 L15 GND L14 L16 L10 L13 VCCIO K11 K14 K13 GND K15 VCCIO K16 GND J16 J15 J14 Ball/Pad Function PB61B PB62A PB63A VCCIO4 PB62B PB63B GNDIO4 PB64A PB64B CFG2 CFG1 PROGRAMN CFG0 PR44B INITN PR43B GNDIO8 CCLK PR44A DONE PR42B VCCIO8 PR43A PR42A PR41B GNDIO8 PR40A PR41A PR39B PR40B VCCIO8 PR39A PR38B PR38A GNDIO8 PR31B VCCIO3 PR31A GNDIO3 PR30B PR30A RLM0_PLLCAP Bank 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 Dual Function BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 VREF2_4/BDQ60 VREF1_4/BDQ60 Differential C T T C C T C WRITEN CSN C C CS1N D1 D0/SPIFASTN D2 D3 D6 D4 D7 D5 DI/CSSPI0N DOUT/CSON BUSY/SISPI RLM0_GPLLC_FB_A/RDQ34 RLM0_GPLLT_FB_A/RDQ34 RLM0_GPLLC_IN_A**/RDQ34 RLM0_GPLLT_IN_A**/RDQ34 T C T T C T T C C T C T C T C (LVDS)* T (LVDS)* 4-42 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number J13 J12 H12 GND H13 H15 VCCIO H16 H11 J11 G16 GND G15 F15 G11 F14 VCCIO F12 G14 G13 GND F16 F9 E16 F10 VCCIO D16 D15 C15 C16 GND D14 B16 F13 VCCIO E13 F11 E11 GND A15 E12 B15 Ball Number J13 J12 H12 GND H13 H15 VCCIO H16 H11 J11 G16 GND G15 F15 G11 F14 VCCIO F12 G14 G13 GND F16 F9 E16 F10 VCCIO D16 D15 C15 C16 GND D14 B16 F13 VCCIO E13 F11 E11 GND A15 E12 B15 Ball/Pad Function PR28B PR28A PR27B GNDIO3 PR27A PR22B VCCIO3 PR22A PR21B PR21A PR19B GNDIO2 PR19A PR17B PR18B PR17A VCCIO2 PR18A PR16B PR16A GNDIO2 PR14B PR15B PR14A PR15A VCCIO2 PR13B PR13A PR6B PR7B GNDIO2 PR6A PR7A PR2B VCCIO2 PR2A PT64B PT64A GNDIO1 PT63B PT62B PT63A Bank 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 Dual Function RLM0_GDLLC_FB_A/RDQ25 RLM0_GDLLT_FB_A/RDQ25 RLM0_GDLLC_IN_A**/RDQ25 RLM0_GDLLT_IN_A**/RDQ25 VREF2_3/RDQ25 VREF1_3/RDQ25 PCLKC3_0/RDQ25 PCLKT3_0/RDQ25 PCLKC2_0/RDQ16 PCLKT2_0/RDQ16 RDQ16 RDQ16 RDQ16 RDQ16 RDQ16 RDQS16 RDQ16 RDQ16 RDQ16 RDQ16 RDQ16 RDQ16 RDQ8 RDQ8 RDQ8 RDQ8 VREF2_2 VREF1_2 VREF2_1 VREF1_1 Differential C T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T C C (LVDS)* T T (LVDS)* C (LVDS)* T (LVDS)* C (LVDS)* C T (LVDS)* T C T C (LVDS)* C T (LVDS)* T C (LVDS)* T (LVDS)* C T C C T 4-43 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number VCCIO D12 B14 C14 A14 D13 C13 GND A13 B13 VCCIO A12 B11 D11 A11 C11 D10 C10 GND B10 A9 A10 B9 VCCIO A8 D9 B8 C9 GND B7 E9 A7 D8 VCCIO A6 B6 E6 F8 GND E8 Ball Number VCCIO D12 B14 C14 A14 D13 C13 GND A13 B13 VCCIO A12 B11 D11 A11 C11 GND VCC D10 C10 GND B10 A9 A10 B9 VCCIO A8 D9 B8 C9 GND B7 E9 A7 D8 VCCIO A6 B6 E6 F8 GND E8 Ball/Pad Function VCCIO1 PT62A PT61B PT60B PT61A PT60A PT59B GNDIO1 PT58B PT59A VCCIO1 PT58A PT57B PT56B PT57A PT56A GNDIO1 VCCIO PT46B PT46A GNDIO1 PT45B PT44B PT45A PT44A VCCIO1 PT43B PT42B PT43A PT42A GNDIO1 PT41B PT40B PT41A PT40A VCCIO1 PT39B PT39A XRES PT37B GNDIO0 PT37A Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Dual Function Differential T C C T T C C T T C C T T C T C C T T C C T T C C T T PCLKC1_0 PCLKT1_0 PCLKC0_0 PCLKT0_0 C T C T 4-44 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number A5 A3 A4 VCCIO B3 A2 C7 B2 D7 D6 GND F7 C6 VCCIO F6 C4 B4 D5 E5 G7 G9 H7 J10 K10 K8 G8 H10 J7 K9 C5 E7 C12 E10 E14 G12 K12 M14 M10 P12 M7 Ball Number A5 A3 A4 VCCIO B3 A2 C7 B2 D7 D6 GND F7 C6 VCCIO F6 C4 B4 GND VCC D5 E5 G7 G9 H7 J10 K10 K8 G8 H10 J7 K9 C5 E7 C12 E10 E14 G12 K12 M14 M10 P12 M7 Ball/Pad Function PT36B PT35B PT36A VCCIO0 PT35A PT34B PT33B PT34A PT33A PT32B GNDIO0 PT31B PT32A VCCIO0 PT31A PT30B PT30A GNDIO0 VCCIO PT2B PT2A VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 2 3 3 4 4 5 Dual Function Differential C C T T C C T T C C T T C T VREF2_0 VREF1_0 C T 4-45 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.) LFE2-20E/SE Ball Number P5 K5 M3 E3 G5 T15 A1 A16 B12 B5 C8 E15 E2 H14 H8 H9 J3 J8 J9 M15 M2 P9 R12 R5 T1 T16 Ball Number P5 K5 M3 E3 G5 T15 A1 A16 B12 B5 C8 E15 E2 H14 H8 H9 J3 J8 J9 M15 M2 P9 R12 R5 T1 T16 Ball/Pad Function VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 5 6 6 7 7 8 - Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-46 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number E4 E5 E3 F4 F3 F5 VCCIO E2 G6 E1 G7 GNDIO F1 H4 F2 H5 G1 G3 G2 G4 J4 H1 J5 L6 VCCIO J2 L5 J1 K3 GNDIO K4 K2 VCCIO K1 L4 GNDIO L3 L2 L1 M5 VCCIO M6 Ball/Pad Function PL2A PL2B NC PL3A NC PL3B VCCIO7 PL4A PL5A PL4B PL5B GNDIO7 NC NC NC NC NC NC NC NC PL7A PL6A PL7B PL9A VCCIO7 PL8A PL9B PL8B PL10A GNDIO7 PL10B PL11A VCCIO7 PL11B PL12A GNDIO7 PL12B PL13A PL13B PL15A VCCIO6 PL15B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 PCLKC6_0 C (LVDS)* LDQ10 PCLKT7_0/LDQ10 PCLKC7_0/LDQ10 PCLKT6_0 C (LVDS)* T C T (LVDS)* LDQ10 LDQ10 C T (LVDS)* LDQ10 LDQ10 C (LVDS)* T LDQ10 LDQ10 LDQ10 LDQS10 T (LVDS)* C C (LVDS)* T (LVDS)* LDQ10 LDQ10 LDQ10 LDQ10 C T T T (LVDS)* T C (LVDS)* C C T Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* Ball/Pad Function PL2A PL2B GNDIO7 PL4A PL5A PL4B PL5B VCCIO7 PL6A PL7A PL6B PL7B GNDIO7 PL9A PL8A PL9B VCCIO7 PL8B PL11A PL10A PL11B GNDIO PL10B PL13A PL12A PL13B PL15A VCCIO7 PL14A PL15B PL14B PL16A GNDIO PL16B PL17A VCCIO7 PL17B PL18A GNDIO PL18B PL19A PL19B PL21A PL21B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 PCLKC6_0/LDQ25 C (LVDS)* LDQ16 PCLKT7_0/LDQ16 PCLKC7_0/LDQ16 PCLKT6_0/LDQ25 C (LVDS)* T C T (LVDS)* LDQ16 LDQ16 C T (LVDS)* LDQ16 LDQ16 C (LVDS)* T LDQ16 LDQ16 LDQ16 LDQS16 T (LVDS)* C C (LVDS)* T (LVDS)* LDQ8 LDQ16 LDQ16 LDQ16 LDQ16 C (LVDS)* T T (LVDS)* C T LDQ8 LDQ8 LDQ8 LDQ8 C (LVDS)* T T (LVDS)* C LDQ8 LDQS8 LDQ8 T T (LVDS)* C LDQ8 LDQ8 LDQ8 LDQ8 T (LVDS)* T C (LVDS)* C LDQ8 LDQ8 LDQ8 LDQ8 T (LVDS)* T C (LVDS)* C LFE2-20E/20SE Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* 4-47 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number M3 GNDIO M4 N1 M2 N2 M1 N3 N5 N4 P5 P1 P2 P4 R4 P6 R1 GNDIO R3 R2 T4 T5 VCCIO T1 T3 T2 GNDIO V1 V2 U1 U3 VCCIO U2 U4 R6 R7 GNDIO T7 T6 Ball/Pad Function PL16A GNDIO6 PL16B NC NC NC NC NC NC NC NC PL17A PL17B PL18A PL18B LLM0_PLLCAP PL20A GNDIO6 PL21A PL20B PL21B PL23A VCCIO6 PL22A PL23B PL22B GNDIO6 PL25A PL25B PL24A PL27A VCCIO6 PL24B PL27B PL26A PL29A GNDIO6 PL29B PL26B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ28 LDQ28 C C (LVDS)* LDQ28 LDQ28 LDQ28 LDQ28 C (LVDS)* C T (LVDS)* T LDQ28 LDQ28 LDQ28 C T (LVDS)* T LDQ28 T T (LVDS)* C C (LVDS)* LLM0_GPLLT_FB_A LLM0_GPLLC_IN_A** LLM0_GPLLC_FB_A T C (LVDS)* C T LLM0_GPLLT_IN_A** T (LVDS)* LLM0_GDLLC_FB_A C LLM0_GDLLT_IN_A** LLM0_GDLLC_IN_A** LLM0_GDLLT_FB_A T (LVDS)* C (LVDS)* T VREF1_6 C Dual Function VREF2_6 Differential T Ball/Pad Function PL22A PL22B VCCIO6 PL24A PL23A PL24B PL23B GNDIO PL25A PL26A PL25B VCCIO6 PL26B PL27A PL27B PL28A GNDIO PL28B LLM0_PLLCAP PL30A PL31A PL30B PL31B PL33A VCCIO6 PL32A PL33B PL32B GNDIO6 VCCIO6 PL39A GNDIO PL39B PL38A PL41A VCCIO6 PL38B PL41B PL40A PL43A GNDIO PL43B PL40B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ42 LDQ42 C C (LVDS)* LDQ42 LDQ42 LDQ42 LDQ42 C (LVDS)* C T (LVDS)* T LDQ42 LDQ42 LDQ42 C T (LVDS)* T LDQ42 T LDQ34 LDQ34 LDQ34 T (LVDS)* C C (LVDS)* LLM0_GPLLT_FB_A/LDQ34 LLM0_GPLLC_IN_A/LDQ34 LLM0_GPLLC_FB_A/LDQ34 LDQ34 T C (LVDS)* C T LLM0_GPLLT_IN_A**/LDQ34 T (LVDS)* LLM0_GDLLC_FB_A/LDQ25 C LDQ25 LLM0_GDLLT_IN_A**/LDQ25 LLM0_GDLLC_IN_A**/LDQ25 LLM0_GDLLT_FB_A/LDQ25 C T (LVDS)* C (LVDS)* T LDQS25 LDQ25 LDQ25 T (LVDS)* T C (LVDS)* LDQ25 LDQ25 LDQ25 LDQ25 T T (LVDS)* C C (LVDS)* VREF1_6/LDQ25 C LFE2-20E/20SE Dual Function VREF2_6/LDQ25 Differential T 4-48 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number AA2 VCCIO Y1 AA1 W1 V3 GNDIO V4 U5 U7 V6 V5 T8 W4 Y3 W3 Y2 AB3 VCCIO W5 AB2 W6 AB5 GNDIO Y4 AB4 AA3 AB6 VCCIO AA5 AA6 Y5 GNDIO Y6 W7 Y7 W8 U8 VCCIO AA7 U9 AB7 Y8 GNDIO Ball/Pad Function PL31A VCCIO6 PL28A PL31B PL28B PL30B GNDIO6 PL30A TDI TCK TDO TMS VCCJ PB3A PB2A PB3B PB2B PB5A VCCIO5 PB4A PB5B PB4B PB7A GNDIO5 PB6A PB7B PB6B PB9A VCCIO5 PB8A PB9B PB8B GNDIO5 PB12A PB11A PB12B PB11B PB14A VCCIO5 PB13A PB14B PB13B PB16A GNDIO5 Bank 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ15 BDQ15 BDQ15 BDQ15 T C C T BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 T T C C T BDQ6 BDQ6 BDQ6 T C C BDQS6 BDQ6 BDQ6 BDQ6 T C C T BDQ6 BDQ6 BDQ6 BDQ6 T C C T BDQ6 VREF2_5/BDQ6 BDQ6 VREF1_5/BDQ6 BDQ6 T T C C T LDQ28 T (LVDS)* LDQS28 LDQ28 LDQ28 LDQ28 T (LVDS)* C C (LVDS)* C (LVDS)* Dual Function LDQ28 Differential T Ball/Pad Function PL45A VCCIO6 PL42A PL45B PL42B PL44B GNDIO PL44A TDI TCK TDO TMS VCCJ PB3A PB2A PB3B PB2B PB5A VCCIO5 PB4A PB5B PB4B PB7A GNDIO PB6A PB7B PB6B PB9A VCCIO5 PB8A PB9B PB8B GNDIO VCCIO5 PB21A PB20A PB21B PB20B PB23A VCCIO5 PB22A PB23B PB22B PB25A GNDIO Bank 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ24 BDQ24 BDQ24 BDQ24 T C C T BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 T T C C T BDQ6 BDQ6 BDQ6 T C C BDQS6 BDQ6 BDQ6 BDQ6 T C C T BDQ6 BDQ6 BDQ6 BDQ6 T C C T BDQ6 VREF2_5/BDQ6 BDQ6 VREF1_5/BDQ6 BDQ6 T T C C T LDQ42 T (LVDS)* LDQS42 LDQ42 LDQ42 LDQ42 T (LVDS)* C C (LVDS)* C (LVDS)* LFE2-20E/20SE Dual Function LDQ42 Differential T 4-49 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number W9 AA8 V9 AB8 VCCIO W10 AA9 V10 GNDIO Y10 AB9 AA10 AB10 AB11 U10 VCCIO AA11 U11 GNDIO AB12 Y11 AA12 W11 AB13 VCCIO AB14 GNDIO Y12 W12 VCCIO U12 V12 U13 GNDIO AA13 U14 Y13 AB16 VCCIO AB15 AB17 AA14 W13 GNDIO W14 Ball/Pad Function PB15A PB16B PB15B PB18A VCCIO5 PB17A PB18B PB17B GNDIO5 PB21A PB20A PB21B PB20B PB23A PB22A VCCIO5 PB23B PB22B GNDIO5 PB25A PB24A PB25B PB24B PB26A VCCIO5 PB26B GNDIO5 PB32A PB32B VCCIO4 PB31A PB31B PB34A GNDIO4 PB33A PB34B PB33B PB36A VCCIO4 PB35A PB36B PB35B PB37A GNDIO4 PB37B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ33 C BDQ33 BDQ33 BDQ33 BDQ33 T C C T BDQS33 BDQ33 BDQ33 BDQ33 T C C T PCLKT4_0/BDQ33 PCLKC4_0/BDQ33 BDQ33 T C T BDQ33 BDQ33 T C PCLKC5_0/BDQ24 C BDQ24 BDQS24 BDQ24 BDQ24 PCLKT5_0/BDQ24 T T C C T BDQ24 BDQ24 C C BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 T T C C T T BDQ15 BDQ15 BDQ15 T C C Dual Function BDQS15 BDQ15 BDQ15 BDQ15 Differential T C C T Ball/Pad Function PB24A PB25B PB24B PB27A VCCIO5 PB26A PB27B PB26B GNDIO PB30A PB29A PB30B PB29B PB32A PB31A VCCIO5 PB32B PB31B GNDIO5 PB34A PB33A PB34B PB33B PB35A VCCIO5 PB35B GNDIO5 PB41A PB41B VCCIO4 PB40A PB40B PB43A GNDIO4 PB42A PB43B PB42B PB45A VCCIO4 PB44A PB45B PB44B PB46A GNDIO4 PB46B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ42 C BDQ42 BDQ42 BDQ42 BDQ42 T C C T BDQS42 BDQ42 BDQ42 BDQ42 T C C T PCLKT4_0/BDQ42 PCLKC4_0/BDQ42 BDQ42 T C T BDQ42 BDQ42 T C PCLKC5_0/BDQ33 C BDQ33 BDQS33 BDQ33 BDQ33 PCLKT5_0/BDQ33 T T C C T BDQ33 BDQ33 C C BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T T C C T T BDQ24 BDQ24 BDQ24 T C C LFE2-20E/20SE Dual Function BDQS24 BDQ24 BDQ24 BDQ24 Differential T C C T 4-50 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number AB18 AB19 Y15 V14 VCCIO AA15 W15 GNDIO AB20 AA16 AB21 AA17 Y16 U15 VCCIO W16 U16 AA18 AA20 GNDIO V16 V17 AA21 VCCIO Y19 AA22 Y20 Y18 GNDIO Y21 Y17 Y22 W17 VCCIO U18 W18 V18 GNDIO T15 T16 W19 V19 V20 W20 U22 Ball/Pad Function PB39A PB39B PB41A PB40A VCCIO4 PB41B PB40B GNDIO4 PB43A PB42A PB43B PB42B PB45A PB44A VCCIO4 PB45B PB44B PB46A PB46B GNDIO4 PB49A PB49B PB48A VCCIO4 PB51A PB48B PB51B PB50A GNDIO4 PB53A PB50B PB53B PB52A VCCIO4 PB54A PB52B PB54B GNDIO4 PB55A PB55B CFG2 CFG1 PROGRAMN CFG0 PR28B Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 D1/SPID6 C VREF2_4/BDQ51 VREF1_4/BDQ51 T C BDQ51 BDQ51 BDQ51 T C C BDQ51 BDQ51 BDQ51 BDQ51 T C C T BDQS51 BDQ51 BDQ51 BDQ51 T C C T BDQ51 BDQ51 BDQ51 T C T BDQ42 BDQ42 BDQ42 BDQ42 C C T C BDQ42 BDQS42 BDQ42 BDQ42 BDQ42 BDQ42 T T C C T T BDQ42 BDQ42 C C Dual Function BDQ42 BDQ42 BDQ42 BDQ42 Differential T C T T Ball/Pad Function PB48A PB48B PB50A PB49A VCCIO4 PB50B PB49B GNDIO PB52A PB51A PB52B PB51B PB54A PB53A VCCIO4 PB54B PB53B PB55A PB55B GNDIO PB58A PB58B PB57A VCCIO4 PB60A PB57B PB60B PB59A GNDIO4 PB62A PB59B PB62B PB61A VCCIO4 PB63A PB61B PB63B GNDIO4 PB64A PB64B CFG2 CFG1 PROGRAMN CFG0 PR42B Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 D1/SPID6 C VREF2_4/BDQ60 VREF1_4/BDQ60 T C BDQ60 BDQ60 BDQ60 T C C BDQ60 BDQ60 BDQ60 BDQ60 T C C T BDQS60 BDQ60 BDQ60 BDQ60 T C C T BDQ60 BDQ60 BDQ60 T C T BDQ51 BDQ51 BDQ51 BDQ51 C C T C BDQ51 BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 T T C C T T BDQ51 BDQ51 C C LFE2-20E/20SE Dual Function BDQ51 BDQ51 BDQ51 BDQ51 Differential T C T T 4-51 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number V22 R16 GNDIO W22 R17 V21 VCCIO U19 T17 U20 U21 GNDIO T18 T20 T21 T19 VCCIO T22 R18 R19 GNDIO P18 R22 P19 R21 VCCIO R20 P22 P21 N21 N17 N22 M22 GNDIO N20 M21 N19 M19 J22 L22 H22 K22 Ball/Pad Function INITN PR30B GNDIO8 CCLK PR30A DONE VCCIO8 PR29B PR26B PR29A PR28A GNDIO8 PR26A PR27B PR25B PR27A VCCIO8 PR25A PR24B PR24A GNDIO3 PR22B PR23B PR22A PR23A VCCIO3 PR21B PR21A PR20B PR20A RLM0_PLLCAP PR18B PR17B GNDIO3 PR18A PR17A NC NC NC NC NC NC Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RLM0_GDLLT_FB_A RLM0_GDLLT_IN_A** T T (LVDS)* RLM0_GDLLC_FB_A RLM0_GDLLC_IN_A** C C (LVDS)* RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A RLM0_GPLLC_IN_A** RLM0_GPLLT_IN_A** C T C (LVDS)* T (LVDS)* C (LVDS)* C T (LVDS)* T DI/CSSPI0N DOUT/CSON BUSY/SISPI T C T D6 D3 D7 D4 T C C T CSN D5 D0/SPIFASTN D2 C C T T CS1N T WRITEN C Dual Function Differential Ball/Pad Function INITN PR44B GNDIO8 CCLK PR44A DONE VCCIO8 PR43B PR40B PR43A PR42A GNDIO8 PR40A PR41B PR39B PR41A VCCIO8 PR39A PR38B PR38A VCCIO3 GNDIO3 PR32B PR33B PR32A PR33A VCCIO3 PR31B PR31A PR30B PR30A RLM0_PLLCAP PR28B PR27B GNDIO3 PR28A PR27A PR26B VCCIO3 PR26A PR23B GNDIO PR24B PR23A PR24A Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ25 RDQ25 RDQ25 C T (LVDS)* T RDQ25 RDQ25 T C (LVDS)* RLM0_GDLLT_FB_A/RDQ25 RLM0_GDLLT_IN_A**/RDQ25 RDQ25 T T (LVDS)* C RLM0_GDLLC_FB_A/RDQ25 C RLM0_GDLLC_IN_A**/RDQ25 C (LVDS)* RLM0_GPLLC_FB_A/RDQ34 RLM0_GPLLT_FB_A/RDQ34 RLM0_GPLLC_IN_A**/RDQ34 RLM0_GPLLT_IN_A**/RDQ34 C T C (LVDS)* T (LVDS)* RDQ34 RDQ34 RDQ34 RDQ34 C (LVDS)* C T (LVDS)* T DI/CSSPI0N DOUT/CSON BUSY/SISPI T C T D6 D3 D7 D4 T C C T CSN D5 D0/SPIFASTN D2 C C T T CS1N T WRITEN C LFE2-20E/20SE Dual Function Differential 4-52 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number M20 VCCIO L21 K21 J21 M18 GNDIO L17 L19 K18 L20 VCCIO K19 L18 K17 GNDIO J17 G22 J18 F22 VCCIO H21 K20 G21 J19 D22 F21 E21 E22 H19 G20 G19 F20 G17 GNDIO E20 F19 D20 F18 VCCIO C21 F16 C22 Ball/Pad Function PR16B VCCIO3 PR16A PR15B PR15A PR13B GNDIO2 PR13A PR12B PR10B PR12A VCCIO2 PR10A PR11B PR11A GNDIO2 PR8B PR9B PR8A PR9A VCCIO2 PR6B PR7B PR6A PR7A NC NC NC NC NC NC NC NC PR5B GNDIO2 PR4B PR5A PR4A PR3B VCCIO2 NC PR3A NC Bank 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T C (LVDS)* T T (LVDS)* C C RDQ10 RDQ10 RDQ10 RDQ10 C (LVDS)* C T (LVDS)* T RDQ10 RDQ10 RDQ10 RDQ10 C (LVDS)* C T (LVDS)* T RDQS10 RDQ10 RDQ10 T (LVDS)* C T PCLKT2_0/RDQ10 RDQ10 RDQ10 RDQ10 T C (LVDS)* C (LVDS)* T (LVDS)* VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ10 T C (LVDS)* T (LVDS)* C Dual Function VREF2_3 Differential C Ball/Pad Function PR22B VCCIO3 PR22A PR21B PR21A PR19B GNDIO2 PR19A PR18B PR16B PR18A VCCIO2 PR16A PR17B PR17A GNDIO2 PR14B PR15B PR14A PR15A VCCIO2 PR12B PR13B PR12A PR13A PR10B PR11B GNDIO PR10A PR11A PR8B PR9B VCCIO2 PR8A PR9A PR7B GNDIO2 PR6B PR7A PR6A PR5B VCCIO2 PR4B PR5A PR4A Bank 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ8 RDQ8 RDQ8 C (LVDS)* T T (LVDS)* RDQ8 RDQ8 RDQ8 RDQ8 C (LVDS)* T T (LVDS)* C RDQS8 RDQ8 RDQ8 T (LVDS)* T C RDQ8 RDQ8 RDQ8 RDQ8 T (LVDS)* T C (LVDS)* C RDQ16 RDQ16 RDQ16 RDQ16 RDQ8 RDQ8 C (LVDS)* C T (LVDS)* T C (LVDS)* C RDQ16 RDQ16 RDQ16 RDQ16 C (LVDS)* C T (LVDS)* T RDQS16 RDQ16 RDQ16 T (LVDS)* C T PCLKT2_0/RDQ16 RDQ16 RDQ16 RDQ16 T C (LVDS)* C (LVDS)* T (LVDS)* VREF1_3/RDQ25 PCLKC3_0/RDQ25 PCLKT3_0/RDQ25 PCLKC2_0/RDQ16 T C (LVDS)* T (LVDS)* C LFE2-20E/20SE Dual Function VREF2_3/RDQ25 Differential C 4-53 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number D19 E19 B21 B22 GNDIO D18 C20 E18 C19 VCCIO D17 B20 C18 A19 GNDIO A18 A21 B18 A20 VCCIO D16 G16 E16 G15 C17 GNDIO C16 A17 B17 A16 VCCIO B16 E15 C15 F15 D15 B15 GNDIO A15 VCCIO A14 B14 D14 E14 Ball/Pad Function PR2B PR2A PT55B PT55A GNDIO1 PT53B PT54B PT53A PT54A VCCIO1 PT51B PT52B PT51A PT52A GNDIO1 PT49B PT50B PT49A PT50A VCCIO1 PT47B PT48B PT47A PT48A PT46B GNDIO1 PT46A PT44B PT45B PT44A VCCIO1 PT45A PT42B PT43B PT42A PT43A PT40B GNDIO1 PT40A VCCIO1 PT39A PT39B PT37B PT36B Bank 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C C C T T C C T T C T C C T C C T T C C C T T C C T T C C T T VREF2_2 VREF1_2 VREF2_1 VREF1_1 C (LVDS)* T (LVDS)* C T Dual Function Differential Ball/Pad Function GNDIO PR2B PR2A PT64B PT64A GNDIO1 PT62B PT63B PT62A PT63A VCCIO1 PT60B PT61B PT60A PT61A GNDIO1 PT58B PT59B PT58A PT59A VCCIO1 PT56B PT57B PT56A PT57A PT55B GNDIO1 PT55A PT53B PT54B PT53A VCCIO1 PT54A PT51B PT52B PT51A PT52A PT49B GNDIO1 PT49A VCCIO1 PT48A PT48B PT46B PT45B Bank 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C C C T T C C T T C T C C T C C T T C C C T T C C T T C C T T VREF2_2 VREF1_2 VREF2_1 VREF1_1 C (LVDS)* T (LVDS)* C T LFE2-20E/20SE Dual Function Differential 4-54 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number GNDIO C13 F14 A13 E13 VCCIO B13 D13 E12 GNDIO D12 A12 B12 VCCIO A11 C12 F12 B10 GNDIO B11 C11 A10 C10 VCCIO A9 A8 E11 A7 F11 GNDIO B8 VCCIO B9 C8 B7 D8 A6 GNDIO C7 D10 C6 E10 VCCIO F10 B6 Ball/Pad Function GNDIO1 PT37A PT36A PT35B PT34B VCCIO1 PT35A PT34A PT33B GNDIO1 PT33A PT31B PT30B VCCIO1 PT31A PT30A XRES PT28B GNDIO0 PT28A PT26B PT27B PT26A VCCIO0 PT27A PT24B PT25B PT24A PT25A GNDIO0 PT23B VCCIO0 PT23A PT20B PT21B PT20A PT21A GNDIO0 PT17B PT18B PT17A PT18A VCCIO0 PT15B PT16B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C C C T T T C C T T C T C C T T PCLKT0_0 T C C T PCLKC0_0 C PCLKT1_0 T T PCLKC1_0 T C C T T C T T C C Dual Function Differential Ball/Pad Function GNDIO1 PT46A PT45A PT44B PT43B VCCIO1 PT44A PT43A PT42B GNDIO1 PT42A PT40B PT39B VCCIO1 PT40A PT39A XRES PT37B GNDIO0 PT37A PT35B PT36B PT35A VCCIO0 PT36A PT33B PT34B PT33A PT34A GNDIO0 PT32B VCCIO0 PT32A PT29B PT30B PT29A PT30A GNDIO0 PT26B PT27B PT26A PT27A VCCIO0 PT24B PT25B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C C C T T T C C T T C T C C T T PCLKT0_0 T C C T PCLKC0_0 C PCLKT1_0 T T PCLKC1_0 T C C T T C T T C C LFE2-20E/20SE Dual Function Differential 4-55 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number D9 B5 GNDIO A5 F9 A4 E9 VCCIO G8 A3 E8 A2 GNDIO C3 B3 E7 F8 F7 D7 VCCIO D4 D5 C4 D6 GNDIO J7 B2 H7 B1 VCCIO D1 D3 C1 C2 J10 J11 J12 J13 K14 K9 L14 L9 M14 Ball/Pad Function PT15A PT16A GNDIO0 PT13B PT14B PT13A PT14A VCCIO0 PT11B PT12B PT11A PT12A GNDIO0 PT10B PT10A PT8B PT9B PT8A PT9A VCCIO0 PT6B PT7B PT6A PT7A GNDIO0 PT4B PT5B PT4A PT5A VCCIO0 PT2B PT3B PT2A PT3A VCC VCC VCC VCC VCC VCC VCC VCC VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF1_0 VREF2_0 C C T T C C T T C C T T C C T T C T C C T T C C T T Dual Function Differential T T Ball/Pad Function PT24A PT25A GNDIO0 PT22B PT23B PT22A PT23A VCCIO0 PT20B PT21B PT20A PT21A GNDIO0 VCCIO0 PT10B PT10A GNDIO0 PT8B PT9B PT8A PT9A VCCIO0 PT6B PT7B PT6A PT7A GNDIO PT4B PT5B PT4A PT5A VCCIO0 PT2B PT3B PT2A PT3A VCC VCC VCC VCC VCC VCC VCC VCC VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF1_0 VREF2_0 C C T T C C T T C C T T C C T T C T C C T T C C T T LFE2-20E/20SE Dual Function Differential T T 4-56 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number M9 N14 N9 P10 P11 P12 P13 G10 G9 H9 H8 G11 G12 G13 G14 H14 H15 J15 K16 L16 M16 N16 P16 R14 T12 T13 T14 R9 T10 T11 T9 N7 P7 P8 R8 J8 K7 L7 M7 P15 R15 C5 D11 E17 E6 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX Bank 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 Dual Function Differential Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX Bank 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 LFE2-20E/20SE Dual Function Differential 4-57 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number F13 G18 G5 K5 M17 P17 R5 V11 V13 V15 V7 V8 A1 A22 AA19 AA4 AB1 AB22 B19 B4 C14 C9 D2 D21 F17 F6 H10 H11 H12 H13 J14 J20 J3 J9 K10 K11 K12 K13 K15 K8 L10 L11 L12 L13 L15 Ball/Pad Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential Ball/Pad Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LFE2-20E/20SE Dual Function Differential 4-58 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA LFE2-12E/12SE Ball Number L8 M10 M11 M12 M13 M15 M8 N10 N11 N12 N13 N15 N8 P14 P20 P3 P9 R10 R11 R12 R13 U17 U6 W2 W21 Y14 Y9 H6 J6 H3 H2 H17 H16 H20 H18 K6 J16 N18 N6 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC VCC VCC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC VCC VCC Bank LFE2-20E/20SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-59 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number E4 E5 VCCIO GNDIO E3 F3 F4 F5 E2 VCCIO E1 G6 G7 H4 GNDIO H5 F1 F2 VCCIO G3 G4 G1 G2 GNDIO H6 J6 H3 H2 H1 J4 J5 VCCIO J2 J1 L6 L5 GNDIO K3 K4 K2 VCCIO K1 L4 Ball/Pad Function PL2A PL2B VCCIO7 GNDIO7 PL10A PL10B PL11A PL11B PL12A VCCIO7 PL12B PL13A PL13B PL14A GNDIO7 PL14B PL15A PL15B VCCIO7 PL16A PL16B PL17A PL17B GNDIO7 NC NC NC NC PL18A PL19A PL19B VCCIO7 PL20A PL20B PL21A PL21B GNDIO7 PL22A PL22B PL23A VCCIO7 PL23B PL24A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ22 LDQ22 C T (LVDS)* LDQS22 LDQ22 LDQ22 T (LVDS)* C (LVDS)* T LDQ22 LDQ22 LDQ22 LDQ22 T (LVDS)* C (LVDS)* T C LDQ22 LDQ22 LDQ22 T C LDQ14 LDQ14 LDQ14 LDQ14 T (LVDS)* C (LVDS)* T C LDQ14 LDQ14 LDQ14 C (LVDS)* T C LDQ14 LDQ14 LDQ14 LDQS14 C (LVDS)* T C T (LVDS)* LDQ14 LDQ14 LDQ14 LDQ14 LDQ14 T (LVDS)* C (LVDS)* T C T (LVDS)* Dual Function VREF2_7/LDQ6 VREF1_7/LDQ6 Differential T (LVDS)* C (LVDS)* Ball/Pad Function PL2A PL2B GNDIO7 VCCIO PL12A PL12B PL13A PL13B PL14A VCCIO PL14B PL15A PL15B PL16A GNDIO7 PL16B PL17A PL17B VCCIO PL18A PL18B PL19A PL19B GNDIO7 VCCIO PL25A VCCIO PL25B PL26A PL26B GNDIO7 VCCIO PL37A PL38A PL38B VCCIO PL39A PL39B PL40A PL40B GNDIO7 PL41A PL41B PL42A VCCIO PL42B PL43A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ41 LDQ41 C T (LVDS)* LDQS41 LDQ41 LDQ41 T (LVDS)* C (LVDS)* T LDQ41 LDQ41 LDQ41 LDQ41 T (LVDS)* C (LVDS)* T C LDQ41 LDQ41 LDQ41 T C LUM0_SPLLC_IN_A/LDQ24 LUM0_SPLLT_FB_A/LDQ24 LUM0_SPLLC_FB_A/LDQ24 C T C LUM0_SPLLT_IN_A/LDQ24 T LDQ16 LDQ16 LDQ16 LDQ16 T (LVDS)* C (LVDS)* T C LDQ16 LDQ16 LDQ16 C (LVDS)* T C LDQ16 LDQ16 LDQ16 LDQS16 C (LVDS)* T C T (LVDS)* LDQ16 LDQ16 LDQ16 LDQ16 LDQ16 T (LVDS)* C (LVDS)* T C T (LVDS)* LFE2-50E/SE Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* 4-60 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number L3 L2 GNDIO L1 M5 M6 M3 M4 M2 VCCIO M1 N1 N2 GNDIO VCCIO N3 N4 N5 VCCIO P5 P1 P2 P4 GNDIO R4 P6 R1 R2 R3 T4 T1 VCCIO T2 T5 T3 GNDIO VCCIO U1 U2 V1 V2 VCCIO R6 T6 U3 U4 GNDIO Ball/Pad Function PL24B PL25A GNDIO7 PL25B PL27A PL27B PL28A PL28B PL29A VCCIO6 PL29B PL30A PL30B GNDIO6 VCCIO6 PL39A PL39B PL40A VCCIO6 PL40B PL41A PL41B PL42A GNDIO6 PL42B LLM0_PLLCAP PL44A PL44B PL45A PL45B PL46A VCCIO6 PL46B PL47A PL47B GNDIO6 VCCIO6 PL52A PL52B PL53A PL53B VCCIO6 PL54A PL54B PL55A PL55B GNDIO6 Bank 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ56 LDQ56 LDQ56 LDQ56 T (LVDS)* C (LVDS)* T C LDQ56 LDQ56 LDQ56 LDQ56 T (LVDS)* C (LVDS)* T C LDQ48 LDQ48 LDQ48 C (LVDS)* T C LLM0_GPLLT_IN_A**/LDQ48 LLM0_GPLLC_IN_A**/LDQ48 LLM0_GPLLT_FB_A/LDQ48 LLM0_GPLLC_FB_A/LDQ48 LDQ48 T (LVDS)* C (LVDS)* T C T (LVDS)* LLM0_GDLLC_FB_A/LDQ39 C LDQ39 LLM0_GDLLT_IN_A**/LDQ39 LLM0_GDLLC_IN_A**/LDQ39 LLM0_GDLLT_FB_A/LDQ39 C T (LVDS)* C (LVDS)* T LDQS39*** LDQ39 LDQ39 T (LVDS)* C (LVDS)* T LDQ31 LDQ31 LDQ31 C (LVDS)* T C PCLKC7_0/LDQ22 PCLKT6_0/LDQ31 PCLKC6_0/LDQ31 VREF2_6/LDQ31 VREF1_6/LDQ31 LDQ31 C T (LVDS)* C (LVDS)* T C T (LVDS)* Dual Function LDQ22 PCLKT7_0/LDQ22 Differential C (LVDS)* T Ball/Pad Function PL43B PL44A GNDIO7 PL44B PL46A PL46B PL47A PL47B PL48A VCCIO PL48B PL49A PL49B GNDIO6 VCCIO PL58A PL58B PL59A VCCIO PL59B PL60A PL60B PL61A GNDIO6 PL61B LLM0_PLLCAP PL63A PL63B PL64A PL64B PL65A VCCIO PL65B PL66A PL66B VCCIO GNDIO6 PL71A PL71B PL72A PL72B VCCIO PL73A PL73B PL74A PL74B GNDIO6 Bank 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ75 LDQ75 LDQ75 LDQ75 T (LVDS)* C (LVDS)* T C LDQ75 LDQ75 LDQ75 LDQ75 T (LVDS)* C (LVDS)* T C LDQ67 LDQ67 LDQ67 C (LVDS)* T C LLM0_GPLLT_IN_A**/LDQ67 LLM0_GPLLC_IN_A**/LDQ67 LLM0_GPLLT_FB_A/LDQ67 LLM0_GPLLC_FB_A/LDQ67 LDQ67 T (LVDS)* C (LVDS)* T C T (LVDS)* LLM0_GDLLC_FB_D/LDQ58 C LDQ58 LLM0_GDLLT_IN_A**/LDQ58 LLM0_GDLLC_IN_A**/LDQ58 LLM0_GDLLT_FB_A/LDQ58 C T (LVDS)* C (LVDS)* T LDQS58*** LDQ58 LDQ58 T (LVDS)* C (LVDS)* T LDQ50 LDQ50 LDQ50 C (LVDS)* T C PCLKC7_0/LDQ41 PCLKT6_0/LDQ50 PCLKC6_0/LDQ50 VREF2_6/LDQ50 VREF1_6/LDQ50 LDQ50 C T (LVDS)* C (LVDS)* T C T (LVDS)* LFE2-50E/SE Dual Function LDQ41 PCLKT7_0/LDQ41 Differential C (LVDS)* T 4-61 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number Y1 W1 R7 VCCIO T7 V4 V3 AA2 GNDIO AA1 U7 U5 V5 V6 T8 Y3 Y2 W4 W3 W5 W6 VCCIO AB3 AB2 GNDIO Y4 AA3 AB5 AB4 AA5 Y5 VCCIO AB6 AA6 GNDIO VCCIO W7 W8 Y6 Y7 AA7 VCCIO AB7 U8 U9 W9 GNDIO Ball/Pad Function PL56A PL56B PL57A VCCIO6 PL57B PL58A PL58B PL59A GNDIO6 PL59B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B GNDIO5 PB6A PB6B PB7A PB7B PB8A PB8B VCCIO5 PB9A PB9B GNDIO5 VCCIO5 PB20A PB20B PB21A PB21B PB22A VCCIO5 PB22B PB23A PB23B PB24A GNDIO5 Bank 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ24 BDQ24 BDQ24 BDQS24 C T C T BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 T C T C T BDQ6 BDQ6 T C BDQS6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C BDQ6 BDQ6 T C VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ56 C LDQ56 LDQ56 LDQ56 LDQ56 C T (LVDS)* C (LVDS)* T Dual Function LDQS56 LDQ56 LDQ56 Differential T (LVDS)* C (LVDS)* T Ball/Pad Function PL75A PL75B PL76A VCCIO PL76B PL77A PL77B PL78A GNDIO6 PL78B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO PB5A PB5B GNDIO5 PB6A PB6B PB7A PB7B PB8A PB8B VCCIO PB9A PB9B GNDIO5 VCCIO PB29A PB29B PB30A PB30B PB31A VCCIO PB31B PB32A PB32B PB33A GNDIO5 Bank 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ33 BDQ33 BDQ33 BDQS33 C T C T BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T BDQ6 BDQ6 T C BDQS6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C BDQ6 BDQ6 T C VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ75 C LDQ75 LDQ75 LDQ75 LDQ75 C T (LVDS)* C (LVDS)* T LFE2-50E/SE Dual Function LDQS75 LDQ75 LDQ75 Differential T (LVDS)* C (LVDS)* T 4-62 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number V9 Y8 AA8 W10 VCCIO V10 AB8 AA9 GNDIO AB9 AB10 Y10 AA10 U10 U11 VCCIO AB11 AA11 GNDIO Y11 W11 AB12 AA12 AB13 AB14 VCCIO GNDIO U12 VCCIO V12 Y12 W12 AA13 GNDIO Y13 U13 U14 AB15 VCCIO AA14 AB16 AB17 W13 GNDIO W14 AB18 AB19 Ball/Pad Function PB24B PB25A PB25B PB26A VCCIO5 PB26B PB27A PB27B GNDIO5 PB29A PB29B PB30A PB30B PB31A PB31B VCCIO5 PB32A PB32B GNDIO5 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO5 GNDIO5 PB40A VCCIO4 PB40B PB41A PB41B PB42A GNDIO4 PB42B PB43A PB43B PB44A VCCIO4 PB44B PB45A PB45B PB46A GNDIO4 PB46B PB48A PB48B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ42 BDQ51 BDQ51 C T C BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 BDQ42 BDQ42 C T C T PCLKC4_0/BDQ42 BDQ42 BDQ42 BDQS42 C T C T PCLKT4_0/BDQ42 T BDQS33 BDQ33 BDQ33 BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 T C T C T C BDQ33 BDQ33 T C BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C BDQ24 BDQ24 BDQ24 C T C Dual Function BDQ24 BDQ24 BDQ24 BDQ24 Differential C T C T Ball/Pad Function PB33B PB34A PB34B PB35A VCCIO PB35B PB36A PB36B GNDIO5 PB38A PB38B PB39A PB39B PB40A PB40B VCCIO PB41A PB41B GNDIO5 PB42A PB42B PB43A PB43B PB44A PB44B VCCIO GNDIO5 PB49A VCCIO PB49B PB50A PB50B PB51A GNDIO4 PB51B PB52A PB52B PB53A VCCIO PB53B PB54A PB54B PB55A GNDIO4 PB55B PB57A PB57B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ51 BDQ60 BDQ60 C T C BDQ51 BDQ51 BDQ51 BDQ51 C T C T BDQ51 BDQ51 BDQ51 BDQ51 C T C T PCLKC4_0/BDQ51 BDQ51 BDQ51 BDQS51 C T C T PCLKT4_0/BDQ51 T BDQS42 BDQ42 BDQ42 BDQ42 PCLKT5_0/BDQ42 PCLKC5_0/BDQ42 T C T C T C BDQ42 BDQ42 T C BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 T C T C T C BDQ33 BDQ33 BDQ33 C T C LFE2-50E/SE Dual Function BDQ33 BDQ33 BDQ33 BDQ33 Differential C T C T 4-63 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number V14 W15 VCCIO Y15 AA15 GNDIO AA16 AA17 AB20 AB21 U15 U16 VCCIO Y16 W16 AA18 AA20 GNDIO VCCIO AA21 AA22 V16 V17 VCCIO Y18 Y17 GNDIO Y19 Y20 W17 W18 Y21 Y22 VCCIO U18 V18 T15 T16 GNDIO W19 V19 W20 V20 W22 V22 V21 GNDIO Ball/Pad Function PB49A PB49B VCCIO4 PB50A PB50B GNDIO4 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO4 PB54A PB54B PB55A PB55B GNDIO4 VCCIO4 PB66A PB66B PB67A PB67B VCCIO4 PB68A PB68B GNDIO4 PB69A PB69B PB70A PB70B PB71A PB71B VCCIO4 PB72A PB72B PB73A PB73B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 BDQ69 BDQ69 VREF2_4/BDQ69 VREF1_4/BDQ69 T C T C BDQS69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ69 BDQ69 T C BDQ69 BDQ69 BDQ69 BDQ69 T C T C BDQ51 BDQ51 BDQ51 BDQ51 T C T C BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ51 BDQ51 T C Dual Function BDQ51 BDQ51 Differential T C Ball/Pad Function PB58A PB58B VCCIO PB59A PB59B GNDIO4 PB60A PB60B PB61A PB61B PB62A PB62B VCCIO PB63A PB63B PB64A PB64B GNDIO4 VCCIO PB75A PB75B PB76A PB76B VCCIO PB77A PB77B GNDIO4 PB78A PB78B PB79A PB79B PB80A PB80B VCCIO PB81A PB81B PB82A PB82B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 BDQ78 BDQ78 VREF2_4/BDQ78 VREF1_4/BDQ78 T C T C BDQS78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T C BDQ78 BDQ78 T C BDQ78 BDQ78 BDQ78 BDQ78 T C T C BDQ60 BDQ60 BDQ60 BDQ60 T C T C BDQS60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T C BDQ60 BDQ60 T C LFE2-50E/SE Dual Function BDQ60 BDQ60 Differential T C 4-64 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number R16 R17 U19 U20 VCCIO U22 U21 T20 GNDIO T19 T17 T18 T21 VCCIO T22 R18 R19 GNDIO VCCIO R22 R21 P18 P19 VCCIO R20 P22 P21 N21 N17 N22 N20 GNDIO M22 M21 N19 M19 VCCIO GNDIO L22 K22 J22 H22 VCCIO M20 L21 K21 J21 Ball/Pad Function PR58B PR58A PR57B PR57A VCCIO8 PR56B PR56A PR55B GNDIO8 PR55A PR54B PR54A PR53B VCCIO8 PR53A PR52B PR52A GNDIO3 VCCIO3 PR47B PR47A PR46B PR46A VCCIO3 PR45B PR45A PR44B PR44A RLM0_PLLCAP PR42B PR42A GNDIO3 PR41B PR41A PR40B PR40A VCCIO3 GNDIO3 PR30B PR30A PR29B PR29A VCCIO3 PR28B PR28A PR27B PR27A Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF2_3/RDQ31 VREF1_3/RDQ31 PCLKC3_0/RDQ31 PCLKT3_0/RDQ31 C T C (LVDS)* T (LVDS)* RDQ31 RDQ31 RDQ31 RDQ31 C T C (LVDS)* T (LVDS)* RLM0_GDLLC_IN_A**/RDQ39 RLM0_GDLLT_IN_A**/RDQ39 RDQ39 RDQ39 C (LVDS)* T (LVDS)* C T RLM0_GDLLC_FB_A/RDQ39 RLM0_GDLLT_FB_A/RDQ39 C T RLM0_GPLLC_FB_A/RDQ48 RLM0_GPLLT_FB_A/RDQ48 RLM0_GPLLC_IN_A**/RDQ48 RLM0_GPLLT_IN_A**/RDQ48 C T C (LVDS)* T (LVDS)* RDQ48 RDQ48 RDQ48 RDQ48 C T C (LVDS)* T (LVDS)* DI/CSSPI0N DOUT/CSON BUSY/SISPI T C T D4 D5 D6 D7 T C T C D1 D2 D3 C T C Dual Function WRITEN CS1N CSN D0/SPIFASTN Differential C T C T Ball/Pad Function PR77B PR77A PR76B PR76A VCCIO PR75B PR75A PR74B GNDIO8 PR74A PR73B PR73A PR72B VCCIO PR72A PR71B PR71A GNDIO3 VCCIO PR66B PR66A PR65B PR65A VCCIO PR64B PR64A PR63B PR63A RLM0_PLLCAP PR61B PR61A GNDIO3 PR60B PR60A PR59B PR59A VCCIO GNDIO3 PR49B PR49A PR48B PR48A VCCIO PR47B PR47A PR46B PR46A Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF2_3/RDQ50 VREF1_3/RDQ50 PCLKC3_0/RDQ50 PCLKT3_0/RDQ50 C T C (LVDS)* T (LVDS)* RDQ50 RDQ50 RDQ50 RDQ50 C T C (LVDS)* T (LVDS)* RLM0_GDLLC_IN_A**/RDQ58 RLM0_GDLLT_IN_A**/RDQ58 RDQ58 RDQ58 C (LVDS)* T (LVDS)* C T RLM0_GDLLC_FB_A/RDQ58 RLM0_GDLLT_FB_A/RDQ58 C T RLM0_GPLLC_FB_A/RDQ67 RLM0_GPLLT_FB_A/RDQ67 RLM0_GPLLC_IN_A**/RDQ67 RLM0_GPLLT_IN_A**/RDQ67 C T C (LVDS)* T (LVDS)* RDQ67 RDQ67 RDQ67 RDQ67 C T C (LVDS)* T (LVDS)* DI/CSSPI0N DOUT/CSON BUSY/SISPI T C T D4 D5 D6 D7 T C T C D1 D2 D3 C T C LFE2-50E/SE Dual Function WRITEN CS1N CSN D0/SPIFASTN Differential C T C T 4-65 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number M18 L17 GNDIO L19 L20 L18 K17 VCCIO K18 K19 G22 GNDIO F22 J17 J18 K20 VCCIO J19 H21 G21 H17 H16 H20 H18 F21 GNDIO E22 D22 E21 G20 VCCIO F20 H19 G19 GNDIO G17 F19 E20 D20 VCCIO F18 F16 C21 Ball/Pad Function PR25B PR25A GNDIO2 PR24B PR24A PR23B PR23A VCCIO2 PR22B PR22A PR21B GNDIO2 PR21A PR20B PR20A PR19B VCCIO2 PR19A PR18B PR18A NC NC NC NC PR17B GNDIO2 PR17A PR16B PR16A PR15B VCCIO2 PR15A PR14B PR14A GNDIO2 PR13B PR13A PR12B PR12A VCCIO2 PR11B PR11A PR10B Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ14 RDQ14 RDQ14 C T C (LVDS)* RDQ14 RDQ14 RDQ14 RDQ14 C T C (LVDS)* T (LVDS)* RDQ14 RDQ14 RDQS14 T C (LVDS)* T (LVDS)* RDQ14 RDQ14 RDQ14 RDQ14 T C (LVDS)* T (LVDS)* C RDQ14 C RDQ22 RDQ22 RDQ22 T C (LVDS)* T (LVDS)* RDQ22 RDQ22 RDQ22 RDQ22 T C (LVDS)* T (LVDS)* C RDQ22 RDQS22 RDQ22 C (LVDS)* T (LVDS)* C RDQ22 RDQ22 RDQ22 RDQ22 C (LVDS)* T (LVDS)* C T Dual Function PCLKC2_0/RDQ22 PCLKT2_0/RDQ22 Differential C T Ball/Pad Function PR44B PR44A GNDIO2 PR43B PR43A PR42B PR42A VCCIO PR41B PR41A PR40B GNDIO2 PR40A PR39B PR39A PR38B VCCIO PR38A PR37B PR37A GNDIO2 VCCIO PR26B PR26A PR25B PR25A GNDIO2 VCCIO PR19B GNDIO2 PR19A PR18B PR18A PR17B VCCIO PR17A PR16B PR16A GNDIO2 PR15B PR15A PR14B PR14A VCCIO PR13B PR13A PR12B Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ16 RDQ16 RDQ16 C T C (LVDS)* RDQ16 RDQ16 RDQ16 RDQ16 C T C (LVDS)* T (LVDS)* RDQ16 RDQ16 RDQS16 T C (LVDS)* T (LVDS)* RDQ16 RDQ16 RDQ16 RDQ16 T C (LVDS)* T (LVDS)* C RDQ16 C RUM0_SPLLC_FB_A/RDQ24 RUM0_SPLLT_FB_A/RDQ24 RUM0_SPLLC_IN_A/RDQ24 RUM0_SPLLT_IN_A/RDQ24 C T C T RDQ41 RDQ41 RDQ41 T C (LVDS)* T (LVDS)* RDQ41 RDQ41 RDQ41 RDQ41 T C (LVDS)* T (LVDS)* C RDQ41 RDQS41 RDQ41 C (LVDS)* T (LVDS)* C RDQ41 RDQ41 RDQ41 RDQ41 C (LVDS)* T (LVDS)* C T LFE2-50E/SE Dual Function PCLKC2_0/RDQ41 PCLKT2_0/RDQ41 Differential C T 4-66 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number C22 VCCIO GNDIO D19 E19 B21 GNDIO B22 C20 C19 D18 VCCIO E18 B20 A19 D17 C18 A21 GNDIO A20 A18 VCCIO B18 G16 G15 D16 E16 GNDIO VCCIO C17 GNDIO C16 B17 B16 A17 VCCIO A16 C15 D15 E15 F15 GNDIO B15 VCCIO A15 B14 A14 Ball/Pad Function PR10A VCCIO2 GNDIO2 PR2B PR2A PT73B GNDIO1 PT73A PT72B PT72A PT71B VCCIO1 PT71A PT70B PT70A PT69B PT69A PT68B GNDIO1 PT68A PT67B VCCIO1 PT67A PT66B PT66A PT65B PT65A GNDIO1 VCCIO1 PT55B GNDIO1 PT55A PT54B PT54A PT53B VCCIO1 PT53A PT52B PT52A PT51B PT51A GNDIO1 PT49B VCCIO1 PT49A PT48B PT48A Bank 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T C T T C T C C T C T C T T C T C T C T C VREF1_1 T C T C VREF2_2/RDQ6 VREF1_2/RDQ6 VREF2_1 C (LVDS)* T (LVDS)* C Dual Function RDQ14 Differential T (LVDS)* Ball/Pad Function PR12A VCCIO GNDIO2 PR2B PR2A PT82B GNDIO1 PT82A PT81B PT81A PT80B VCCIO PT80A PT79B PT79A PT78B PT78A PT77B GNDIO1 PT77A PT76B VCCIO PT76A PT75B PT75A PT74B PT74A GNDIO1 VCCIO PT64B GNDIO1 PT64A PT63B PT63A PT62B VCCIO PT62A PT61B PT61A PT60B PT60A GNDIO1 PT58B VCCIO PT58A PT57B PT57A Bank 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T C T T C T C C T C T C T T C T C T C T C VREF1_1 T C T C VREF2_2 VREF1_2 VREF2_1 C (LVDS)* T (LVDS)* C LFE2-50E/SE Dual Function RDQ16 Differential T (LVDS)* 4-67 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number D14 C13 GNDIO E14 F14 A13 B13 VCCIO E13 D13 E12 D12 GNDIO A12 A11 VCCIO B12 C12 F12 B10 GNDIO B11 A10 A9 C11 VCCIO C10 E11 F11 A8 A7 B8 GNDIO B9 VCCIO B7 A6 C8 D8 GNDIO D10 E10 C7 C6 VCCIO B6 B5 Ball/Pad Function PT46B PT46A GNDIO1 PT45B PT45A PT44B PT44A VCCIO1 PT43B PT43A PT42B PT42A GNDIO1 PT40B PT40A VCCIO1 PT39B PT39A XRES PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A PT32B GNDIO0 PT32A VCCIO0 PT30B PT30A PT29B PT29A GNDIO0 PT27B PT27A PT26B PT26A VCCIO0 PT25B PT25A Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T T T C T C T C PCLKT0_0 T C T C PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T C T C T C T C T C T Dual Function Differential C T Ball/Pad Function PT55B PT55A GNDIO1 PT54B PT54A PT53B PT53A VCCIO PT52B PT52A PT51B PT51A GNDIO1 PT49B PT49A VCCIO PT48B PT48A XRES PT46B GNDIO0 PT46A PT45B PT45A PT44B VCCIO PT44A PT43B PT43A PT42B PT42A PT41B GNDIO0 PT41A VCCIO PT39B PT39A PT38B PT38A GNDIO0 PT36B PT36A PT35B PT35A VCCIO PT34B PT34A Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T T T C T C T C PCLKT0_0 T C T C PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T C T C T C T C T C T LFE2-50E/SE Dual Function Differential C T 4-68 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number F10 D9 GNDIO F9 E9 A5 A4 VCCIO A3 A2 G8 E8 GNDIO VCCIO C3 B3 GNDIO F8 D7 E7 VCCIO F7 D5 D6 D4 C4 GNDIO B2 B1 J7 VCCIO H7 D3 C2 D1 C1 J10 J11 J12 J13 K14 K9 L14 L9 M14 M9 N14 Ball/Pad Function PT24B PT24A GNDIO0 PT23B PT23A PT22B PT22A VCCIO0 PT21B PT21A PT20B PT20A GNDIO0 VCCIO0 PT10B PT10A GNDIO0 PT9B PT9A PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A GNDIO0 PT5B PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 T C T C T C T C T C T C T C T C C T C T C T C T C T Dual Function Differential C T Ball/Pad Function PT33B PT33A GNDIO0 PT32B PT32A PT31B PT31A VCCIO PT30B PT30A PT29B PT29A GNDIO0 VCCIO PT10B PT10A GNDIO0 PT9B PT9A PT8B VCCIO PT8A PT7B PT7A PT6B PT6A GNDIO0 PT5B PT5A PT4B VCCIO PT4A PT3B PT3A PT2B PT2A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 T C T C T C T C T C T C T C T C C T C T C T C T C T LFE2-50E/SE Dual Function Differential C T 4-69 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number N9 P10 P11 P12 P13 G5 K5 R5 V7 V11 V8 V13 V15 M17 P17 E17 G18 D11 F13 C5 E6 G10 G9 H8 H9 G11 G12 G13 G14 H14 H15 J15 K16 L16 M16 N16 P16 R14 T12 T13 T14 R9 T10 T11 T9 N7 P7 Ball/Pad Function VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 Bank 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 Dual Function Differential Ball/Pad Function VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 Bank 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 LFE2-50E/SE Dual Function Differential 4-70 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number P8 R8 J8 K7 L7 M7 P15 R15 A22 AA19 AA4 AB1 AB22 B19 B4 C14 C9 D2 D21 F17 F6 H10 H11 H12 H13 J14 J20 J3 J9 K10 K11 K12 K13 K15 K8 L10 L11 L12 L13 L15 L8 M10 M11 M12 M13 M15 M8 Ball/Pad Function VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 6 6 7 7 7 7 8 8 Dual Function Differential Ball/Pad Function VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 6 6 7 7 7 7 8 8 LFE2-50E/SE Dual Function Differential 4-71 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA LFE2-35E/SE Ball Number N10 N11 N12 N13 N15 N8 P14 P20 P3 P9 R10 R11 R12 R13 U17 U6 W2 W21 Y14 Y9 A1 N18 K6 N6 J16 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCPLL NC VCCPLL NC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCPLL VCCPLL VCCPLL VCCPLL Bank LFE2-50E/SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-72 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number D2 D1 GND F6 F5 VCCIO E4 E3 E2 E1 GND H6 H5 F2 VCCIO F1 H8 J9 G4 GND G3 H7 J8 G2 G1 H3 VCCIO H4 J5 J4 J3 GND K4 H1 H2 VCCIO K6 K7 J1 J2 GND VCCIO K3 K2 GND K1 L2 Ball/Pad Function PL2A PL2B GNDIO7 PL3A PL3B VCCIO7 NC NC NC NC GNDIO7 NC NC NC VCCIO7 NC NC NC NC GNDIO7 NC PL4A PL4B PL5A PL5B PL6A VCCIO7 PL6B PL7A PL7B PL8A GNDIO7 PL8B PL9A PL9B VCCIO7 PL10A PL10B PL11A PL11B GNDIO7 VCCIO7 NC NC GNDIO7 NC NC Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ8 LDQ8 LDQ8 LDQ8 T (LVDS)* C (LVDS)* T C LDQ8 LDQ8 LDQ8 C (LVDS)* T C LDQ8 LDQ8 LDQ8 LDQS8 C (LVDS)* T C T (LVDS)* LDQ8 LDQ8 LDQ8 LDQ8 LDQ8 T (LVDS)* C (LVDS)* T C T (LVDS)* T C Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* Ball/Pad Function PL2A PL2B GNDIO7 PL3A PL3B VCCIO7 PL4A PL4B PL5A PL5B GNDIO7 PL6A PL6B PL7A VCCIO7 PL7B PL8A PL8B PL9A GNDIO7 PL9B PL10A PL10B PL11A PL11B PL12A VCCIO7 PL12B PL13A PL13B PL14A GNDIO7 PL14B PL15A PL15B VCCIO7 PL16A PL16B PL17A PL17B GNDIO7 VCCIO7 NC NC GNDIO7 NC NC Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ14 LDQ14 LDQ14 LDQ14 T (LVDS)* C (LVDS)* T C LDQ14 LDQ14 LDQ14 C (LVDS)* T C LDQ14 LDQ14 LDQ14 LDQS14 C (LVDS)* T C T (LVDS)* LDQ6 LDQ14 LDQ14 LDQ14 LDQ14 LDQ14 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ6 LDQ6 LDQ6 LDQ6 C T (LVDS)* C (LVDS)* T LDQS6 LDQ6 LDQ6 T (LVDS)* C (LVDS)* T LDQ6 LDQ6 LDQ6 LDQ6 T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 T C LFE2-35E/35SE Dual Function VREF2_7/LDQ6 VREF1_7/LDQ6 Differential T (LVDS)* C (LVDS)* 4-73 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number L1 VCCIO M2 M1 N2 GND M8 VCCIO GND N1 L8 K8 VCCIO L6 K5 L7 L5 GND P1 P2 M6 VCCIO N8 R1 R2 M7 GND N9 M4 M5 N7 P9 N3 VCCIO N4 N5 P7 T1 GND T2 P8 P6 VCCIO P5 P4 U1 V1 Ball/Pad Function NC VCCIO7 NC NC NC GNDIO7 VCC VCCIO7 GNDIO7 PL12A PL13A PL13B VCCIO7 PL14A PL14B PL15A PL15B GNDIO7 PL16A PL16B PL17A VCCIO7 PL17B PL18A PL18B PL19A GNDIO7 PL19B PL21A PL21B PL22A PL22B PL23A VCCIO6 PL23B PL24A PL24B NC GNDIO6 NC NC NC VCCIO6 NC NC NC NC Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 LDQ25 LDQ25 LDQ25 C (LVDS)* T C PCLKC7_0/LDQ16 PCLKT6_0/LDQ25 PCLKC6_0/LDQ25 VREF2_6/LDQ25 VREF1_6/LDQ25 LDQ25 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ16 LDQ16 LDQ16 PCLKT7_0/LDQ16 C T (LVDS)* C (LVDS)* T LDQS16 LDQ16 LDQ16 T (LVDS)* C (LVDS)* T LDQ16 LDQ16 LDQ16 LDQ16 T (LVDS)* C (LVDS)* T C LDQ16 LDQ16 LDQ16 T C Dual Function Differential Ball/Pad Function NC VCCIO7 NC NC NC GNDIO7 NC VCCIO7 GNDIO7 PL18A PL19A PL19B VCCIO7 PL20A PL20B PL21A PL21B GNDIO7 PL22A PL22B PL23A VCCIO7 PL23B PL24A PL24B PL25A GNDIO7 PL25B PL27A PL27B PL28A PL28B PL29A VCCIO6 PL29B PL30A PL30B PL31A GNDIO6 PL31B PL32A PL32B VCCIO6 PL33A PL33B PL34A PL34B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ31 LDQ31 LDQ31 LDQ31 T (LVDS)* C (LVDS)* T C LDQ31 LDQ31 LDQ31 C (LVDS)* T C LDQ31 LDQ31 LDQ31 LDQS31 C (LVDS)* T C T (LVDS)* PCLKC7_0/LDQ22 PCLKT6_0/LDQ31 PCLKC6_0/LDQ31 VREF2_6/LDQ31 VREF1_6/LDQ31 LDQ31 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ22 LDQ22 LDQ22 PCLKT7_0/LDQ22 C T (LVDS)* C (LVDS)* T LDQS22 LDQ22 LDQ22 T (LVDS)* C (LVDS)* T LDQ22 LDQ22 LDQ22 LDQ22 T (LVDS)* C (LVDS)* T C LDQ22 LDQ22 LDQ22 T C LFE2-35E/35SE Dual Function Differential 4-74 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number GND P3 R3 R4 U2 VCCIO V2 W2 T6 R5 GND R6 R7 W1 VCCIO Y2 Y1 AA2 T5 GND T7 R8 T8 U3 U4 V3 U5 V4 VCCIO V5 Y3 Y4 W3 GND W4 AA1 AB1 VCCIO U8 U7 V8 U6 GND W6 W5 AC1 AD1 Ball/Pad Function GNDIO6 NC NC NC NC VCCIO6 NC NC NC NC GNDIO6 PL25A PL25B PL26A VCCIO6 PL26B PL27A PL27B PL28A GNDIO6 PL28B VCC LLM0_PLLCAP PL30A PL30B PL31A PL31B PL32A VCCIO6 PL32B PL33A PL33B PL34A GNDIO6 PL34B PL35A PL35B VCCIO6 PL36A PL36B PL37A PL37B GNDIO6 PL38A PL38B PL39A PL39B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ42 LDQ42 LDQ42 LDQ42 T (LVDS)* C (LVDS)* T C LDQ34 LDQ34 LDQ34 LDQ34 T (LVDS)* C (LVDS)* T C LDQ34 LDQ34 LDQ34 C (LVDS)* T C LDQ34 LDQ34 LDQ34 LDQS34 C (LVDS)* T C T (LVDS)* LLM0_GPLLT_IN_A**/LDQ34 LLM0_GPLLC_IN_A**/LDQ34 LLM0_GPLLT_FB_A/LDQ34 LLM0_GPLLC_FB_A/LDQ34 LDQ34 T (LVDS)* C (LVDS)* T C T (LVDS)* LLM0_GDLLC_FB_A/LDQ25 C LDQ25 LLM0_GDLLT_IN_A**/LDQ25 LLM0_GDLLC_IN_A**/LDQ25 LLM0_GDLLT_FB_A/LDQ25 C T (LVDS)* C (LVDS)* T LDQS25*** LDQ25 LDQ25 T (LVDS)* C (LVDS)* T Dual Function Differential Ball/Pad Function GNDIO6 NC NC NC NC VCCIO6 NC NC PL38A PL38B GNDIO6 PL39A PL39B PL40A VCCIO6 PL40B PL41A PL41B PL42A GNDIO6 PL42B VCCPLL LLM0_PLLCAP PL44A PL44B PL45A PL45B PL46A VCCIO6 PL46B PL47A PL47B PL48A GNDIO6 PL48B PL49A PL49B VCCIO6 PL50A PL50B PL51A PL51B GNDIO6 PL52A PL52B PL53A PL53B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ56 LDQ56 LDQ56 LDQ56 T (LVDS)* C (LVDS)* T C LDQ48 LDQ48 LDQ48 LDQ48 T (LVDS)* C (LVDS)* T C LDQ48 LDQ48 LDQ48 C (LVDS)* T C LDQ48 LDQ48 LDQ48 LDQS48 C (LVDS)* T C T (LVDS)* LLM0_GPLLT_IN_A**/LDQ48 LLM0_GPLLC_IN_A**/LDQ48 LLM0_GPLLT_FB_A/LDQ48 LLM0_GPLLC_FB_A/LDQ48 LDQ48 T (LVDS)* C (LVDS)* T C T (LVDS)* LLM0_GDLLC_FB_A/LDQ39 C LDQ39 LLM0_GDLLT_IN_A**/LDQ39 LLM0_GDLLC_IN_A**/LDQ39 LLM0_GDLLT_FB_A/LDQ39 C T (LVDS)* C (LVDS)* T LDQS39*** LDQ39 LDQ39 T (LVDS)* C (LVDS)* T LDQ39 LDQ39 T C LFE2-35E/35SE Dual Function Differential 4-75 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number VCCIO Y6 Y5 AE2 AD2 GND AB3 AB2 W7 VCCIO W8 Y7 Y8 AC2 GND AD3 AC3 AA8 AB4 AA5 AB5 AE3 AF3 AC4 AD4 AE4 AF4 VCCIO V9 W9 GND AA6 AB6 AC5 AD5 AA7 AB7 VCCIO AE5 AF5 AC7 AD7 VCCIO GND W10 Y10 W11 Ball/Pad Function VCCIO6 PL40A PL40B PL41A PL41B GNDIO6 PL42A PL42B PL43A VCCIO6 PL43B PL44A PL44B PL45A GNDIO6 PL45B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B GNDIO5 PB6A PB6B PB7A PB7B PB8A PB8B VCCIO5 PB9A PB9B PB10A PB10B VCCIO5 GNDIO5 PB11A PB11B PB12A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ15 BDQ15 BDQ15 T C T BDQ6 BDQ6 BDQ6 BDQ6 T C T C BDQS6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C BDQ6 BDQ6 T C VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ42 C LDQ42 LDQ42 LDQ42 LDQ42 C T (LVDS)* C (LVDS)* T LDQS42 LDQ42 LDQ42 T (LVDS)* C (LVDS)* T LDQ42 LDQ42 LDQ42 LDQ42 T (LVDS)* C (LVDS)* T C Dual Function Differential Ball/Pad Function VCCIO6 PL54A PL54B PL55A PL55B GNDIO6 PL56A PL56B PL57A VCCIO6 PL57B PL58A PL58B PL59A GNDIO6 PL59B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B GNDIO5 PB6A PB6B PB7A PB7B PB8A PB8B VCCIO5 PB9A PB9B PB10A PB10B VCCIO5 GNDIO5 PB11A PB11B PB12A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ15 BDQ15 BDQ15 T C T BDQ6 BDQ6 BDQ6 BDQ6 T C T C BDQS6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C BDQ6 BDQ6 T C VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ56 C LDQ56 LDQ56 LDQ56 LDQ56 C T (LVDS)* C (LVDS)* T LDQS56 LDQ56 LDQ56 T (LVDS)* C (LVDS)* T LDQ56 LDQ56 LDQ56 LDQ56 T (LVDS)* C (LVDS)* T C LFE2-35E/35SE Dual Function Differential 4-76 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number AA10 AC8 AD8 VCCIO AB8 AB10 GND AE6 AF6 AA11 AC9 AB9 AD9 VCCIO Y11 AB11 AE7 AF7 GND AC10 AD10 AA12 W12 AB12 VCCIO Y12 AD12 AC12 AC13 GND AA13 AD13 AC14 AE8 VCCIO AF8 AB15 Y13 AE9 GND AF9 W13 AA14 AE10 AF10 W14 AB13 Ball/Pad Function PB12B PB13A PB13B VCCIO5 PB14A PB14B GNDIO5 PB15A PB15B PB16A PB16B PB17A PB17B VCCIO5 PB18A PB18B PB19A PB19B GNDIO5 PB20A PB20B PB21A PB21B PB22A VCCIO5 PB22B PB23A PB23B PB24A GNDIO5 PB24B PB25A PB25B PB26A VCCIO5 PB26B PB27A PB27B PB28A GNDIO5 PB28B PB29A PB29B PB30A PB30B PB31A PB31B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ24 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 C T C T C T C BDQ24 BDQ24 BDQ24 BDQ24 C T C T BDQ24 BDQ24 BDQ24 BDQ24 C T C T BDQ24 BDQ24 BDQ24 BDQS24 C T C T BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 T C T C T BDQ15 BDQ15 BDQ15 BDQ15 T C T C BDQS15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 T C T C T C BDQ15 BDQ15 T C Dual Function BDQ15 BDQ15 BDQ15 Differential C T C Ball/Pad Function PB12B PB13A PB13B VCCIO5 PB14A PB14B GNDIO5 PB15A PB15B PB16A PB16B PB17A PB17B VCCIO5 PB18A PB18B PB19A PB19B GNDIO5 PB20A PB20B PB21A PB21B PB22A VCCIO5 PB22B PB23A PB23B PB24A GNDIO5 PB24B PB25A PB25B PB26A VCCIO5 PB26B PB27A PB27B PB28A GNDIO5 PB28B PB29A PB29B PB30A PB30B PB31A PB31B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ24 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 C T C T C T C BDQ24 BDQ24 BDQ24 BDQ24 C T C T BDQ24 BDQ24 BDQ24 BDQ24 C T C T BDQ24 BDQ24 BDQ24 BDQS24 C T C T BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 T C T C T BDQ15 BDQ15 BDQ15 BDQ15 T C T C BDQS15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 T C T C T C BDQ15 BDQ15 T C LFE2-35E/35SE Dual Function BDQ15 BDQ15 BDQ15 Differential C T C 4-77 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number VCCIO Y14 AB14 GND AE11 AF11 AD14 AA15 AE12 AF12 VCCIO GND AD15 VCCIO AC15 AE13 AF13 AB17 GND Y15 AE14 AF14 AA16 VCCIO W15 AC17 AB16 AE15 GND AF15 AE16 AF16 Y16 AB18 AD17 AD18 VCCIO AC18 AD19 GND AC19 AE17 AB19 AE19 AF17 AE18 VCCIO Ball/Pad Function VCCIO5 PB32A PB32B GNDIO5 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO5 GNDIO5 PB40A VCCIO4 PB40B PB41A PB41B PB42A GNDIO4 PB42B PB43A PB43B PB44A VCCIO4 PB44B PB45A PB45B PB46A GNDIO4 PB46B PB47A PB47B PB48A PB48B PB49A PB49B VCCIO4 PB50A PB50B GNDIO4 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO4 Bank 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ51 BDQ51 T C BDQ42 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 C T C T C T C BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 BDQ42 BDQ42 C T C T PCLKC4_0/BDQ42 BDQ42 BDQ42 BDQS42 C T C T PCLKT4_0/BDQ42 T BDQS33 BDQ33 BDQ33 BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 T C T C T C BDQ33 BDQ33 T C Dual Function Differential Ball/Pad Function VCCIO5 PB32A PB32B GNDIO5 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO5 GNDIO5 PB40A VCCIO4 PB40B PB41A PB41B PB42A GNDIO4 PB42B PB43A PB43B PB44A VCCIO4 PB44B PB45A PB45B PB46A GNDIO4 PB46B PB47A PB47B PB48A PB48B PB49A PB49B VCCIO4 PB50A PB50B GNDIO4 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO4 Bank 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ51 BDQ51 T C BDQ42 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 C T C T C T C BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 BDQ42 BDQ42 C T C T PCLKC4_0/BDQ42 BDQ42 BDQ42 BDQS42 C T C T PCLKT4_0/BDQ42 T BDQS33 BDQ33 BDQ33 BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 T C T C T C BDQ33 BDQ33 T C LFE2-35E/35SE Dual Function Differential 4-78 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number W16 AA17 AF18 AF19 GND AA19 W17 Y19 Y17 AF20 VCCIO AE20 AA20 W18 AD20 GND AE21 AF21 AF22 VCCIO GND AE22 AD22 AF23 AE23 AD23 AC23 VCCIO AB20 AC20 GND AB21 AC22 W19 AA21 AF24 AE24 VCCIO Y20 AB22 Y21 AB23 GND AD24 W20 AC24 V19 Ball/Pad Function PB54A PB54B PB55A PB55B GNDIO4 NC NC NC NC NC VCCIO4 NC NC NC NC GNDIO4 NC NC NC VCCIO4 GNDIO4 PB56A PB56B PB57A PB57B PB58A PB58B VCCIO4 PB59A PB59B GNDIO4 PB60A PB60B PB61A PB61B PB62A PB62B VCCIO4 PB63A PB63B PB64A PB64B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 BDQ60 BDQ60 VREF2_4/BDQ60 VREF1_4/BDQ60 T C T C BDQS60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T C BDQ60 BDQ60 T C BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T C Dual Function BDQ51 BDQ51 BDQ51 BDQ51 Differential T C T C Ball/Pad Function PB54A PB54B PB55A PB55B GNDIO4 PB56A PB56B PB57A PB57B NC VCCIO4 NC NC NC NC GNDIO4 NC NC NC VCCIO4 GNDIO4 PB65A PB65B PB66A PB66B PB67A PB67B VCCIO4 PB68A PB68B GNDIO4 PB69A PB69B PB70A PB70B PB71A PB71B VCCIO4 PB72A PB72B PB73A PB73B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 BDQ69 BDQ69 VREF2_4/BDQ69 VREF1_4/BDQ69 T C T C BDQS69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ69 BDQ69 T C BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ60 BDQ60 BDQ60 BDQ60 T C T C LFE2-35E/35SE Dual Function BDQ51 BDQ51 BDQ51 BDQ51 Differential T C T C 4-79 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number AA22 AB24 AD25 GND W21 Y22 AC25 AB25 VCCIO AD26 AC26 Y23 GND W22 AA25 AB26 W23 VCCIO V22 Y24 Y25 W24 GND V23 AA26 Y26 U21 VCCIO U19 W25 W26 GND V24 V25 V26 U26 VCCIO U22 U23 U24 U25 R20 P18 T19 U20 GND T25 Ball/Pad Function CCLK INITN DONE GNDIO8 PR44B PR44A PR43B PR43A VCCIO8 PR42B PR42A PR41B GNDIO8 PR41A PR40B PR40A PR39B VCCIO8 PR39A PR38B PR38A PR37B GNDIO3 PR37A PR36B PR36A PR35B VCCIO3 PR35A PR34B PR34A GNDIO3 PR33B PR33A PR32B PR32A VCCIO3 PR31B PR31A PR30B PR30A RLM0_PLLCAP VCC PR28B PR28A GNDIO3 PR27B Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RLM0_GDLLC_IN_A**/RDQ25 C (LVDS)* RLM0_GDLLC_FB_A/RDQ25 RLM0_GDLLT_FB_A/RDQ25 C T RLM0_GPLLC_FB_A/RDQ34 RLM0_GPLLT_FB_A/RDQ34 RLM0_GPLLC_IN_A**/RDQ34 RLM0_GPLLT_IN_A**/RDQ34 C T C (LVDS)* T (LVDS)* RDQ34 RDQ34 RDQ34 RDQ34 C T C (LVDS)* T (LVDS)* RDQ34 RDQ34 RDQS34 T C (LVDS)* T (LVDS)* RDQ34 RDQ34 RDQ34 RDQ34 T C (LVDS)* T (LVDS)* C DI/CSSPI0N DOUT/CSON BUSY/SISPI RDQ34 T C T C D4 D5 D6 D7 T C T C D1 D2 D3 C T C WRITEN CS1N CSN D0/SPIFASTN C T C T Dual Function Differential Ball/Pad Function CCLK INITN DONE GNDIO8 PR58B PR58A PR57B PR57A VCCIO8 PR56B PR56A PR55B GNDIO8 PR55A PR54B PR54A PR53B VCCIO8 PR53A PR52B PR52A PR51B GNDIO3 PR51A PR50B PR50A PR49B VCCIO3 PR49A PR48B PR48A GNDIO3 PR47B PR47A PR46B PR46A VCCIO3 PR45B PR45A PR44B PR44A RLM0_PLLCAP VCCPLL PR42B PR42A GNDIO3 PR41B Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RLM0_GDLLC_IN_A**/RDQ39 C (LVDS)* RLM0_GDLLC_FB_A/RDQ39 RLM0_GDLLT_FB_A/RDQ39 C T RLM0_GPLLC_FB_A/RDQ48 RLM0_GPLLT_FB_A/RDQ48 RLM0_GPLLC_IN_A**/RDQ48 RLM0_GPLLT_IN_A**/RDQ48 C T C (LVDS)* T (LVDS)* RDQ48 RDQ48 RDQ48 RDQ48 C T C (LVDS)* T (LVDS)* RDQ48 RDQ48 RDQS48 T C (LVDS)* T (LVDS)* RDQ48 RDQ48 RDQ48 RDQ48 T C (LVDS)* T (LVDS)* C DI/CSSPI0N DOUT/CSON BUSY/SISPI RDQ48 T C T C D4 D5 D6 D7 T C T C D1 D2 D3 C T C WRITEN CS1N CSN D0/SPIFASTN C T C T LFE2-35E/35SE Dual Function Differential 4-80 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number T26 T20 T22 VCCIO R26 R25 R22 GND T21 P26 P25 R24 VCCIO R23 P20 R19 P21 GND P19 P23 P22 N22 VCCIO R21 N26 N25 GND N19 N20 M26 M25 VCCIO N18 N21 L26 L25 N24 M23 GND L21 K22 M24 N23 VCCIO K26 K25 M20 Ball/Pad Function PR27A PR26B PR26A VCCIO3 PR25B PR25A NC GNDIO3 NC NC NC NC VCCIO3 NC NC NC NC GNDIO3 NC NC NC NC VCCIO3 NC NC NC GNDIO3 PR24B PR24A PR23B PR23A VCCIO3 PR22B PR22A PR21B PR21A PR19B PR19A GNDIO2 PR18B PR18A PR17B PR17A VCCIO2 PR16B PR16A PR15B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 RDQ16 RDQS16 RDQ16 C (LVDS)* T (LVDS)* C RDQ16 RDQ16 RDQ16 RDQ16 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ25 VREF1_3/RDQ25 PCLKC3_0/RDQ25 PCLKT3_0/RDQ25 PCLKC2_0/RDQ16 PCLKT2_0/RDQ16 C T C (LVDS)* T (LVDS)* C T RDQ25 RDQ25 RDQ25 RDQ25 C T C (LVDS)* T (LVDS)* RDQ25 RDQS25*** C (LVDS)* T (LVDS)* Dual Function RLM0_GDLLT_IN_A**/RDQ25 RDQ25 RDQ25 Differential T (LVDS)* C T Ball/Pad Function PR41A PR40B PR40A VCCIO3 PR39B PR39A PR38B GNDIO3 PR38A NC NC NC VCCIO3 NC NC NC PR34B GNDIO3 PR34A PR33B PR33A PR32B VCCIO3 PR32A PR31B PR31A GNDIO3 PR30B PR30A PR29B PR29A VCCIO3 PR28B PR28A PR27B PR27A PR25B PR25A GNDIO2 PR24B PR24A PR23B PR23A VCCIO2 PR22B PR22A PR21B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 RDQ22 RDQS22 RDQ22 C (LVDS)* T (LVDS)* C RDQ22 RDQ22 RDQ22 RDQ22 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ31 VREF1_3/RDQ31 PCLKC3_0/RDQ31 PCLKT3_0/RDQ31 PCLKC2_0/RDQ22 PCLKT2_0/RDQ22 C T C (LVDS)* T (LVDS)* C T RDQ31 RDQ31 RDQ31 RDQ31 C T C (LVDS)* T (LVDS)* RDQ31 RDQ31 RDQS31 T C (LVDS)* T (LVDS)* RDQ31 RDQ31 RDQ31 RDQ31 T C (LVDS)* T (LVDS)* C RDQ31 C RDQ39 T RDQ39 RDQS39*** RDQ39 C (LVDS)* T (LVDS)* C LFE2-35E/35SE Dual Function RLM0_GDLLT_IN_A**/RDQ39 RDQ39 RDQ39 Differential T (LVDS)* C T 4-81 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number GND M19 L22 M22 K21 VCCIO M21 K24 J24 GND VCCIO L20 GND J26 J25 J23 K23 VCCIO H26 H25 H24 GND H23 VCCIO G26 GND G25 F26 F25 K20 VCCIO L19 E26 E25 GND J22 H22 G24 G23 VCCIO K19 J19 D26 C26 F22 E24 GND Ball/Pad Function GNDIO2 PR15A PR14B PR14A PR13B VCCIO2 PR13A PR12B PR12A GNDIO2 VCCIO2 VCC GNDIO2 NC NC NC NC VCCIO2 NC NC NC GNDIO2 NC VCCIO2 PR11B GNDIO2 PR11A PR10B PR10A PR9B VCCIO2 PR9A PR8B PR8A GNDIO2 PR7B PR7A PR6B PR6A VCCIO2 PR5B PR5A PR4B PR4A NC NC GNDIO2 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ8 RDQ8 RDQ8 RDQ8 C T C (LVDS)* T (LVDS)* RDQ8 RDQ8 RDQ8 RDQ8 C T C (LVDS)* T (LVDS)* RDQ8 RDQ8 RDQS8 T C (LVDS)* T (LVDS)* RDQ8 RDQ8 RDQ8 RDQ8 T C (LVDS)* T (LVDS)* C RDQ8 C RDQ16 RDQ16 RDQ16 T C (LVDS)* T (LVDS)* RDQ16 RDQ16 RDQ16 RDQ16 T C (LVDS)* T (LVDS)* C Dual Function Differential Ball/Pad Function GNDIO2 PR21A PR20B PR20A PR19B VCCIO2 PR19A PR18B PR18A GNDIO2 VCCIO2 NC GNDIO2 NC NC NC NC VCCIO2 NC NC NC GNDIO2 NC VCCIO2 PR17B GNDIO2 PR17A PR16B PR16A PR15B VCCIO2 PR15A PR14B PR14A GNDIO2 PR13B PR13A PR12B PR12A VCCIO2 PR11B PR11A PR10B PR10A PR9B PR9A GNDIO2 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ14 RDQ14 RDQ14 RDQ14 RDQ6 RDQ6 C T C (LVDS)* T (LVDS)* C T RDQ14 RDQ14 RDQ14 RDQ14 C T C (LVDS)* T (LVDS)* RDQ14 RDQ14 RDQS14 T C (LVDS)* T (LVDS)* RDQ14 RDQ14 RDQ14 RDQ14 T C (LVDS)* T (LVDS)* C RDQ14 C RDQ22 RDQ22 RDQ22 T C (LVDS)* T (LVDS)* RDQ22 RDQ22 RDQ22 RDQ22 T C (LVDS)* T (LVDS)* C LFE2-35E/35SE Dual Function Differential 4-82 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number D25 C25 D24 B25 VCCIO H21 G22 B24 GND C24 D23 C23 G21 VCCIO H20 GND E22 F21 E23 GND D22 G20 J18 F20 VCCIO H19 A24 A23 E21 F19 C22 GND E20 B22 VCCIO B23 C20 D20 A22 A21 GND E19 C19 VCCIO B21 B20 D19 Ball/Pad Function NC NC NC NC VCCIO2 NC NC NC GNDIO2 NC NC NC PR3B VCCIO2 PR3A GNDIO2 PR2B PR2A PT64B GNDIO1 PT64A PT63B PT63A PT62B VCCIO1 PT62A PT61B PT61A PT60B PT60A PT59B GNDIO1 PT59A PT58B VCCIO1 PT58A PT57B PT57A PT56B PT56A GNDIO1 NC NC VCCIO1 NC NC NC Bank 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T T C T C T C T C VREF1_1 T C T C VREF2_2 VREF1_2 VREF2_1 C (LVDS)* T (LVDS)* C T C Dual Function Differential Ball/Pad Function PR8B PR8A PR7B PR7A VCCIO2 PR6B PR6A PR5B GNDIO2 PR5A PR4B PR4A PR3B VCCIO2 PR3A GNDIO2 PR2B PR2A PT73B GNDIO1 PT73A PT72B PT72A PT71B VCCIO1 PT71A PT70B PT70A PT69B PT69A PT68B GNDIO1 PT68A PT67B VCCIO1 PT67A PT66B PT66A PT65B PT65A GNDIO1 NC NC VCCIO1 NC NC NC Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T T C T C T C T C VREF1_1 T C T C VREF2_2/RDQ6 VREF1_2/RDQ6 VREF2_1 C (LVDS)* T (LVDS)* C RDQ6 T RDQ6 RDQ6 RDQ6 RDQ6 T C (LVDS)* T (LVDS)* C RDQ6 RDQS6 RDQ6 C (LVDS)* T (LVDS)* C LFE2-35E/35SE Dual Function RDQ6 RDQ6 RDQ6 RDQ6 Differential C (LVDS)* T (LVDS)* C T 4-83 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number B19 GND G17 E18 G19 F17 VCCIO A20 A19 E17 D18 B18 GND A18 E16 G16 F16 VCCIO H18 A17 B17 C18 B16 C17 GND D17 E15 VCCIO G15 A16 B15 D15 F15 A14 B14 GND C15 A15 A13 B13 VCCIO H17 H15 D13 C14 GND G14 Ball/Pad Function NC GNDIO1 NC NC NC NC VCCIO1 NC NC NC NC PT55B GNDIO1 PT55A PT54B PT54A PT53B VCCIO1 PT53A PT52B PT52A PT51B PT51A PT50B GNDIO1 PT50A PT49B VCCIO1 PT49A PT48B PT48A PT47B PT47A PT46B PT46A GNDIO1 PT45B PT45A PT44B PT44A VCCIO1 PT43B PT43A PT42B PT42A GNDIO1 PT41B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C T C T C T C T T C T C T C T T C T C T C T C T C T C C Dual Function Differential Ball/Pad Function NC GNDIO1 NC NC NC NC VCCIO1 NC NC NC NC PT55B GNDIO1 PT55A PT54B PT54A PT53B VCCIO1 PT53A PT52B PT52A PT51B PT51A PT50B GNDIO1 PT50A PT49B VCCIO1 PT49A PT48B PT48A PT47B PT47A PT46B PT46A GNDIO1 PT45B PT45A PT44B PT44A VCCIO1 PT43B PT43A PT42B PT42A GNDIO1 PT41B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C T C T C T C T T C T C T C T T C T C T C T C T C T C C LFE2-35E/35SE Dual Function Differential 4-84 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number E14 A12 B12 VCCIO F14 D14 H16 H14 GND H13 A11 B11 C13 VCCIO E13 D12 F13 A10 B10 C12 GND C10 G13 VCCIO H12 A9 B9 E12 G12 A8 B8 GND E11 C9 A7 B7 VCCIO F12 D10 H11 G11 GND A6 B6 D8 C8 VCCIO Ball/Pad Function PT41A PT40B PT40A VCCIO1 PT39B PT39A XRES PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A PT32B GNDIO0 PT32A PT31B VCCIO0 PT31A PT30B PT30A PT29B PT29A PT28B PT28A GNDIO0 PT27B PT27A PT26B PT26A VCCIO0 PT25B PT25A PT24B PT24A GNDIO0 PT23B PT23A PT22B PT22A VCCIO0 Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T T C T C T C T T C T C T C T C PCLKT0_0 T C T C PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T Dual Function Differential T C T Ball/Pad Function PT41A PT40B PT40A VCCIO1 PT39B PT39A XRES PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A PT32B GNDIO0 PT32A PT31B VCCIO0 PT31A PT30B PT30A PT29B PT29A PT28B PT28A GNDIO0 PT27B PT27A PT26B PT26A VCCIO0 PT25B PT25A PT24B PT24A GNDIO0 PT23B PT23A PT22B PT22A VCCIO0 Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T T C T C T C T T C T C T C T C PCLKT0_0 T C T C PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T LFE2-35E/35SE Dual Function Differential T C T 4-85 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number F11 E10 E9 D9 G10 GND H10 A5 B5 C7 VCCIO D7 E8 F10 F8 H9 C5 GND D5 B4 VCCIO GND VCCIO GND VCCIO C4 GND C3 A4 A3 B3 VCCIO B2 D4 D3 C2 C1 G8 GND G7 E7 VCCIO F7 E6 E5 G6 G5 Ball/Pad Function PT21B PT21A PT20B PT20A PT19B GNDIO0 PT19A PT18B PT18A PT17B VCCIO0 PT17A PT16B PT16A PT15B PT15A PT14B GNDIO0 PT14A PT13B VCCIO0 GNDIO0 VCCIO0 GNDIO0 VCCIO0 PT10B GNDIO0 PT10A PT9B PT9A PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A PT5B GNDIO0 PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 T C T C T T C T C T C T C T C T C C T T C T C T C T C T C Dual Function Differential C T C T C Ball/Pad Function PT21B PT21A PT20B PT20A PT19B GNDIO0 PT19A PT18B PT18A PT17B VCCIO0 PT17A PT16B PT16A PT15B PT15A PT14B GNDIO0 PT14A PT13B VCCIO0 GNDIO0 VCCIO0 GNDIO0 VCCIO0 PT10B GNDIO0 PT10A PT9B PT9A PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A PT5B GNDIO0 PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 T C T C T T C T C T C T C T C T C C T T C T C T C T C T C LFE2-35E/35SE Dual Function Differential C T C T C 4-86 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number L12 L13 L14 L15 M11 M12 M15 M16 N11 N16 P11 P16 R11 R12 R15 R16 T12 T13 T14 T15 D11 D6 G9 K12 J12 D16 D21 G18 J15 K15 F23 J20 L23 M17 M18 AA23 R17 R18 T23 V20 AC16 AC21 U15 V15 Y18 AC11 AC6 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 Bank 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 Dual Function Differential Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 Bank 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 LFE2-35E/35SE Dual Function Differential 4-87 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number U12 V12 Y9 AA4 R10 R9 T4 V7 F4 J7 L4 M10 M9 AE25 V18 J10 J11 J16 J17 K18 K9 L18 L9 T18 T9 U18 U9 V10 V11 V16 V17 A2 A25 AA18 AA24 AA3 AA9 AD11 AD16 AD21 AD6 AE1 AE26 AF2 AF25 B1 B26 Ball/Pad Function VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 5 5 5 6 6 6 6 6 7 7 7 7 7 8 8 Dual Function Differential Ball/Pad Function VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 5 5 5 6 6 6 6 6 7 7 7 7 7 8 8 LFE2-35E/35SE Dual Function Differential 4-88 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number C11 C16 C21 C6 F18 F24 F3 F9 J13 J14 J21 J6 K10 K11 K13 K14 K16 K17 L10 L11 L16 L17 L24 L3 M13 M14 N10 N12 N13 N14 N15 N17 P10 P12 P13 P14 P15 P17 R13 R14 T10 T11 T16 T17 T24 T3 U10 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LFE2-35E/35SE Dual Function Differential 4-89 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA LFE2-20E/20SE Ball Number U11 U13 U14 U16 U17 V13 V14 V21 V6 M3 N6 P24 Ball/Pad Function GND GND GND GND GND GND GND GND GND NC NC NC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND NC NC NC Bank LFE2-35E/35SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-90 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number D2 D1 GND F6 F5 VCCIO E4 E3 E2 E1 GND H6 H5 F2 VCCIO F1 H8 J9 G4 GND G3 H7 J8 G2 G1 H3 VCCIO H4 J5 J4 J3 GND K4 H1 H2 VCCIO K6 K7 J1 J2 GND VCCIO K3 K2 GND K1 L2 Ball/Pad Function PL2A PL2B GNDIO7 PL5A PL5B VCCIO7 PL6A PL6B PL7A PL7B GNDIO7 PL8A PL8B PL9A VCCIO7 PL9B PL10A PL10B PL11A GNDIO7 PL11B PL12A PL12B PL13A PL13B PL14A VCCIO7 PL14B PL15A PL15B PL16A GNDIO7 PL16B PL17A PL17B VCCIO7 PL18A PL18B PL19A PL19B GNDIO7 VCCIO7 PL23A PL23B GNDIO7 PL24A PL24B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQS24*** LDQ24 T (LVDS)* C (LVDS)* LDQ24 LDQ24 T C LDQ16 LDQ16 LDQ16 LDQ16 T (LVDS)* C (LVDS)* T C LDQ16 LDQ16 LDQ16 C (LVDS)* T C LDQ16 LDQ16 LDQ16 LDQS16 C (LVDS)* T C T (LVDS)* LDQ8 LDQ16 LDQ16 LDQ16 LDQ16 LDQ16 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ8 LDQ8 LDQ8 LDQ8 C T (LVDS)* C (LVDS)* T LDQS8 LDQ8 LDQ8 T (LVDS)* C (LVDS)* T LDQ8 LDQ8 LDQ8 LDQ8 T (LVDS)* C (LVDS)* T C LDQ8 LDQ8 T C Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* Ball/Pad Function PL2A PL2B GNDIO7 PL18A PL18B VCCIO7 PL19A PL19B PL20A PL20B GNDIO7 PL21A PL21B PL22A VCCIO7 PL22B PL23A PL23B PL24A GNDIO7 PL24B PL25A PL25B PL26A PL26B PL27A VCCIO7 PL27B PL28A PL28B PL29A GNDIO7 PL29B PL30A PL30B VCCIO7 PL31A PL31B PL32A PL32B GNDIO7 VCCIO7 PL36A PL36B GNDIO7 PL37A PL37B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQS37*** LDQ37 T (LVDS)* C (LVDS)* LDQ37 LDQ37 T C LDQ29 LDQ29 LDQ29 LDQ29 T (LVDS)* C (LVDS)* T C LDQ29 LDQ29 LDQ29 C (LVDS)* T C LDQ29 LDQ29 LDQ29 LDQS29 C (LVDS)* T C T (LVDS)* LDQ21 LDQ29 LDQ29 LDQ29 LDQ29 LDQ29 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ21 LDQ21 LDQ21 LDQ21 C T (LVDS)* C (LVDS)* T LDQS21 LDQ21 LDQ21 T (LVDS)* C (LVDS)* T LDQ21 LDQ21 LDQ21 LDQ21 T (LVDS)* C (LVDS)* T C LDQ21 LDQ21 T C LFE2-70E/SE Dual Function VREF2_7 VREF1_7 Differential T (LVDS)* C (LVDS)* 4-91 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number L1 VCCIO M2 M1 N2 GND M8 VCCIO GND N1 L8 K8 VCCIO L6 K5 L7 L5 GND P1 P2 M6 VCCIO N8 R1 R2 M7 GND N9 M4 M5 N7 P9 N3 VCCIO N4 N5 P7 T1 GND T2 P8 P6 VCCIO P5 P4 U1 V1 Ball/Pad Function PL25A VCCIO7 PL25B PL26A PL26B GNDIO7 VCCPLL VCCIO7 GNDIO7 PL37A PL38A PL38B VCCIO7 PL39A PL39B PL40A PL40B GNDIO7 PL41A PL41B PL42A VCCIO7 PL42B PL43A PL43B PL44A GNDIO7 PL44B PL46A PL46B PL47A PL47B PL48A VCCIO6 PL48B PL49A PL49B PL50A GNDIO6 PL50B PL51A PL51B VCCIO6 PL52A PL52B PL53A PL53B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ50 LDQ50 LDQ50 LDQ50 T (LVDS)* C (LVDS)* T C LDQ50 LDQ50 LDQ50 C (LVDS)* T C LDQ50 LDQ50 LDQ50 LDQS50 C (LVDS)* T C T (LVDS)* PCLKC7_0/LDQ41 PCLKT6_0/LDQ50 PCLKC6_0/LDQ50 VREF2_6/LDQ50 VREF1_6/LDQ50 LDQ50 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ41 LDQ41 LDQ41 PCLKT7_0/LDQ41 C T (LVDS)* C (LVDS)* T LDQS41 LDQ41 LDQ41 T (LVDS)* C (LVDS)* T LDQ41 LDQ41 LDQ41 LDQ41 T (LVDS)* C (LVDS)* T C LDQ41 LDQ41 LDQ41 T C LUM0_SPLLC_IN_A/LDQ24 LUM0_SPLLT_FB_A/LDQ24 LUM0_SPLLC_FB_A/LDQ24 C T C Dual Function LUM0_SPLLT_IN_A/LDQ24 Differential T Ball/Pad Function PL38A VCCIO7 PL38B PL39A PL39B GNDIO7 NC VCCIO7 GNDIO7 PL50A PL51A PL51B VCCIO7 PL52A PL52B PL53A PL53B GNDIO7 PL54A PL54B PL55A VCCIO7 PL55B PL56A PL56B PL57A GNDIO7 PL57B PL59A PL59B PL60A PL60B PL61A VCCIO6 PL61B PL62A PL62B PL63A GNDIO6 PL63B PL64A PL64B VCCIO6 PL65A PL65B PL66A PL66B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ63 LDQ63 LDQ63 LDQ63 T (LVDS)* C (LVDS)* T C LDQ63 LDQ63 LDQ63 C (LVDS)* T C LDQ63 LDQ63 LDQ63 LDQS63 C (LVDS)* T C T (LVDS)* PCLKC7_0/LDQ54 PCLKT6_0/LDQ63 PCLKC6_0/LDQ63 VREF2_6/LDQ63 VREF1_6/LDQ63 LDQ63 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ54 LDQ54 LDQ54 PCLKT7_0/LDQ54 C T (LVDS)* C (LVDS)* T LDQS54 LDQ54 LDQ54 T (LVDS)* C (LVDS)* T LDQ54 LDQ54 LDQ54 LDQ54 T (LVDS)* C (LVDS)* T C LDQ54 LDQ54 LDQ54 T C LUM0_SPLLC_IN_A/LDQ37 LUM0_SPLLT_FB_A/LDQ37 LUM0_SPLLC_FB_A/LDQ37 C T C LFE2-70E/SE Dual Function LUM0_SPLLT_IN_A/LDQ37 Differential T 4-92 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number GND P3 R3 R4 U2 VCCIO V2 W2 T6 R5 GND R6 R7 W1 VCCIO Y2 Y1 AA2 T5 GND T7 R8 T8 U3 U4 V3 U5 V4 VCCIO V5 Y3 Y4 W3 GND W4 AA1 AB1 VCCIO U8 U7 V8 U6 GND W6 W5 AC1 AD1 Ball/Pad Function GNDIO6 PL54A PL54B PL55A PL55B VCCIO6 PL56A PL56B PL57A PL57B GNDIO6 PL58A PL58B PL59A VCCIO6 PL59B PL60A PL60B PL61A GNDIO6 PL61B VCCPLL LLM0_PLLCAP PL63A PL63B PL64A PL64B PL65A VCCIO6 PL65B PL66A PL66B PL67A GNDIO6 PL67B PL68A PL68B VCCIO6 PL69A PL69B PL70A PL70B GNDIO6 PL71A PL71B PL72A PL72B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ75 LDQ75 LDQ75 LDQ75 T (LVDS)* C (LVDS)* T C LDQ67 LDQ67 LDQ67 LDQ67 T (LVDS)* C (LVDS)* T C LDQ67 LDQ67 LDQ67 C (LVDS)* T C LDQ67 LDQ67 LDQ67 LDQS67 C (LVDS)* T C T (LVDS)* LLM0_GPLLT_IN_A**/LDQ67 LLM0_GPLLC_IN_A**/LDQ67 LLM0_GPLLT_FB_A/LDQ67 LLM0_GPLLC_FB_A/LDQ67 LDQ67 T (LVDS)* C (LVDS)* T C T (LVDS)* LLM0_GDLLC_FB_D/LDQ58 C LDQ58 LLM0_GDLLT_IN_A**/LDQ58 LLM0_GDLLC_IN_A**/LDQ58 LLM0_GDLLT_FB_A/LDQ58 C T (LVDS)* C (LVDS)* T LDQS58 LDQ58 LDQ58 T (LVDS)* C (LVDS)* T LDQ58 LDQ58 LDQ58 LDQ58 T (LVDS)* C (LVDS)* T C LDQ58 LDQ58 LDQ58 LDQ58 T (LVDS)* C (LVDS)* T C Dual Function Differential Ball/Pad Function GNDIO6 PL67A PL67B PL68A PL68B VCCIO6 PL69A PL69B PL70A PL70B GNDIO6 PL71A PL71B PL72A VCCIO6 PL72B PL73A PL73B PL74A GNDIO6 PL74B VCCPLL LLM0_PLLCAP PL76A PL76B PL77A PL77B PL78A VCCIO6 PL78B PL79A PL79B PL80A GNDIO6 PL80B PL81A PL81B VCCIO6 PL82A PL82B PL83A PL83B GNDIO6 PL84A PL84B PL85A PL85B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ88 LDQ88 LDQ88 LDQ88 T (LVDS)* C (LVDS)* T C LDQ80 LDQ80 LDQ80 LDQ80 T (LVDS)* C (LVDS)* T C LDQ80 LDQ80 LDQ80 C (LVDS)* T C LDQ80 LDQ80 LDQ80 LDQS80 C (LVDS)* T C T (LVDS)* LLM0_GPLLT_IN_A**/LDQ80 LLM0_GPLLC_IN_A**/LDQ80 LLM0_GPLLT_FB_A/LDQ80 LLM0_GPLLC_FB_A/LDQ80 LDQ80 T (LVDS)* C (LVDS)* T C T (LVDS)* LLM0_GDLLC_FB_D/LDQ71 C LDQ71 LLM0_GDLLT_IN_A**/LDQ71 LLM0_GDLLC_IN_A**/LDQ71 LLM0_GDLLT_FB_A/LDQ71 C T (LVDS)* C (LVDS)* T LDQS71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T LDQ71 LDQ71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T C LDQ71 LDQ71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T C LFE2-70E/SE Dual Function Differential 4-93 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number VCCIO Y6 Y5 AE2 AD2 GND AB3 AB2 W7 VCCIO W8 Y7 Y8 AC2 GND AD3 AC3 AA8 AB4 AA5 AB5 AE3 AF3 AC4 AD4 AE4 AF4 VCCIO V9 W9 GND AA6 AB6 AC5 AD5 AA7 AB7 VCCIO AE5 AF5 AC7 AD7 VCCIO GND W10 Y10 W11 Ball/Pad Function VCCIO6 PL73A PL73B PL74A PL74B GNDIO6 PL75A PL75B PL76A VCCIO6 PL76B PL77A PL77B PL78A GNDIO6 PL78B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B GNDIO5 PB6A PB6B PB7A PB7B PB8A PB8B VCCIO5 PB9A PB9B PB10A PB10B VCCIO5 GNDIO5 PB20A PB20B PB21A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ24 BDQ24 BDQ24 T C T BDQ6 BDQ6 BDQ6 BDQ6 T C T C BDQS6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C BDQ6 BDQ6 T C VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ75 C LDQ75 LDQ75 LDQ75 LDQ75 C T (LVDS)* C (LVDS)* T LDQS75 LDQ75 LDQ75 T (LVDS)* C (LVDS)* T LDQ75 LDQ75 LDQ75 LDQ75 T (LVDS)* C (LVDS)* T C Dual Function Differential Ball/Pad Function VCCIO6 PL86A PL86B PL87A PL87B GNDIO6 PL88A PL88B PL89A VCCIO6 PL89B PL90A PL90B PL91A GNDIO6 PL91B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B GNDIO5 PB6A PB6B PB7A PB7B PB8A PB8B VCCIO5 PB9A PB9B PB10A PB10B VCCIO5 GNDIO5 PB29A PB29B PB30A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ33 BDQ33 BDQ33 T C T BDQ6 BDQ6 BDQ6 BDQ6 T C T C BDQS6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C BDQ6 BDQ6 T C VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ88 C LDQ88 LDQ88 LDQ88 LDQ88 C T (LVDS)* C (LVDS)* T LDQS88 LDQ88 LDQ88 T (LVDS)* C (LVDS)* T LDQ88 LDQ88 LDQ88 LDQ88 T (LVDS)* C (LVDS)* T C LFE2-70E/SE Dual Function Differential 4-94 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number AA10 AC8 AD8 VCCIO AB8 AB10 GND AE6 AF6 AA11 AC9 AB9 AD9 VCCIO Y11 AB11 AE7 AF7 GND AC10 AD10 AA12 W12 AB12 VCCIO Y12 AD12 AC12 AC13 GND AA13 AD13 AC14 AE8 VCCIO AF8 AB15 Y13 AE9 GND AF9 W13 AA14 AE10 AF10 W14 AB13 Ball/Pad Function PB21B PB22A PB22B VCCIO5 PB23A PB23B GNDIO5 PB24A PB24B PB25A PB25B PB26A PB26B VCCIO5 PB27A PB27B PB28A PB28B GNDIO5 PB29A PB29B PB30A PB30B PB31A VCCIO5 PB31B PB32A PB32B PB33A GNDIO5 PB33B PB34A PB34B PB35A VCCIO5 PB35B PB36A PB36B PB37A GNDIO5 PB37B PB38A PB38B PB39A PB39B PB40A PB40B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ33 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 C T C T C T C BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQS33 C T C T BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T BDQ24 BDQ24 BDQ24 BDQ24 T C T C BDQS24 BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 T C T C T C BDQ24 BDQ24 T C Dual Function BDQ24 BDQ24 BDQ24 Differential C T C Ball/Pad Function PB30B PB31A PB31B VCCIO5 PB32A PB32B GNDIO5 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO5 PB36A PB36B PB37A PB37B GNDIO5 PB38A PB38B PB39A PB39B PB40A VCCIO5 PB40B PB41A PB41B PB42A GNDIO5 PB42B PB43A PB43B PB44A VCCIO5 PB44B PB45A PB45B PB46A GNDIO5 PB46B PB47A PB47B PB48A PB48B PB49A PB49B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ42 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 C T C T C T C BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 BDQ42 BDQS42 C T C T BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 T C T C T BDQ33 BDQ33 BDQ33 BDQ33 T C T C BDQS33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C BDQ33 BDQ33 T C LFE2-70E/SE Dual Function BDQ33 BDQ33 BDQ33 Differential C T C 4-95 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number VCCIO Y14 AB14 GND AE11 AF11 AD14 AA15 AE12 AF12 VCCIO GND AD15 VCCIO AC15 AE13 AF13 AB17 GND Y15 AE14 AF14 AA16 VCCIO W15 AC17 AB16 AE15 GND AF15 AE16 AF16 Y16 AB18 AD17 AD18 VCCIO AC18 AD19 GND AC19 AE17 AB19 AE19 AF17 AE18 VCCIO Ball/Pad Function VCCIO5 PB41A PB41B GNDIO5 PB42A PB42B PB43A PB43B PB44A PB44B VCCIO5 GNDIO5 PB49A VCCIO4 PB49B PB50A PB50B PB51A GNDIO4 PB51B PB52A PB52B PB53A VCCIO4 PB53B PB54A PB54B PB55A GNDIO4 PB55B PB56A PB56B PB57A PB57B PB58A PB58B VCCIO4 PB59A PB59B GNDIO4 PB60A PB60B PB61A PB61B PB62A PB62B VCCIO4 Bank 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQS60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T C BDQ60 BDQ60 T C BDQ51 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 C T C T C T C BDQ51 BDQ51 BDQ51 BDQ51 C T C T BDQ51 BDQ51 BDQ51 BDQ51 C T C T PCLKC4_0/BDQ51 BDQ51 BDQ51 BDQS51 C T C T PCLKT4_0/BDQ51 T BDQS42 BDQ42 BDQ42 BDQ42 PCLKT5_0/BDQ42 PCLKC5_0/BDQ42 T C T C T C BDQ42 BDQ42 T C Dual Function Differential Ball/Pad Function VCCIO5 PB50A PB50B GNDIO5 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO5 GNDIO5 PB58A VCCIO4 PB58B PB59A PB59B PB60A GNDIO4 PB60B PB61A PB61B PB62A VCCIO4 PB62B PB63A PB63B PB64A GNDIO4 PB64B PB65A PB65B PB66A PB66B PB67A PB67B VCCIO4 PB68A PB68B GNDIO4 PB69A PB69B PB70A PB70B PB71A PB71B VCCIO4 Bank 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQS69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ69 BDQ69 T C BDQ60 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 C T C T C T C BDQ60 BDQ60 BDQ60 BDQ60 C T C T BDQ60 BDQ60 BDQ60 BDQ60 C T C T PCLKC4_0/BDQ60 BDQ60 BDQ60 BDQS60 C T C T PCLKT4_0/BDQ60 T BDQS51 BDQ51 BDQ51 BDQ51 PCLKT5_0/BDQ51 PCLKC5_0/BDQ51 T C T C T C BDQ51 BDQ51 T C LFE2-70E/SE Dual Function Differential 4-96 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number W16 AA17 AF18 AF19 GND AA19 W17 Y19 Y17 AF20 VCCIO AE20 AA20 W18 AD20 GND AE21 AF21 AF22 VCCIO GND AE22 AD22 AF23 AE23 AD23 AC23 VCCIO AB20 AC20 GND AB21 AC22 W19 AA21 AF24 AE24 VCCIO Y20 AB22 Y21 AB23 GND AD24 W20 AC24 V19 Ball/Pad Function PB63A PB63B PB64A PB64B GNDIO4 PB65A PB65B PB66A PB66B PB67A VCCIO4 PB67B PB68A PB68B PB69A GNDIO4 PB69B PB70A PB70B VCCIO4 GNDIO4 PB74A PB74B PB75A PB75B PB76A PB76B VCCIO4 PB77A PB77B GNDIO4 PB78A PB78B PB79A PB79B PB80A PB80B VCCIO4 PB81A PB81B PB82A PB82B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 BDQ78 BDQ78 VREF2_4/BDQ78 VREF1_4/BDQ78 T C T C BDQS78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T C BDQ78 BDQ78 T C BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T C BDQ69 BDQ69 BDQ69 C T C BDQ69 BDQ69 BDQ69 BDQS69 C T C T BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T Dual Function BDQ60 BDQ60 BDQ60 BDQ60 Differential T C T C Ball/Pad Function PB72A PB72B PB73A PB73B GNDIO4 PB74A PB74B PB75A PB75B PB76A VCCIO4 PB76B PB77A PB77B PB78A GNDIO4 PB78B PB79A PB79B VCCIO4 GNDIO4 PB92A PB92B PB93A PB93B PB94A PB94B VCCIO4 PB95A PB95B GNDIO4 PB96A PB96B PB97A PB97B PB98A PB98B VCCIO4 PB99A PB99B PB100A PB100B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 BDQ96 BDQ96 VREF2_4/BDQ96 VREF1_4/BDQ96 T C T C BDQS96 BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 T C T C T C BDQ96 BDQ96 T C BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 T C T C T C BDQ78 BDQ78 BDQ78 C T C BDQ78 BDQ78 BDQ78 BDQS78 C T C T BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T LFE2-70E/SE Dual Function BDQ69 BDQ69 BDQ69 BDQ69 Differential T C T C 4-97 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number AA22 AB24 AD25 GND W21 Y22 AC25 AB25 VCCIO AD26 AC26 Y23 GND W22 AA25 AB26 W23 VCCIO V22 Y24 Y25 W24 GND V23 AA26 Y26 U21 VCCIO U19 W25 W26 GND V24 V25 V26 U26 VCCIO U22 U23 U24 U25 R20 P18 T19 U20 GND T25 Ball/Pad Function CCLK INITN DONE GNDIO8 PR77B PR77A PR76B PR76A VCCIO8 PR75B PR75A PR74B GNDIO8 PR74A PR73B PR73A PR72B VCCIO8 PR72A PR71B PR71A PR70B GNDIO3 PR70A PR69B PR69A PR68B VCCIO3 PR68A PR67B PR67A GNDIO3 PR66B PR66A PR65B PR65A VCCIO3 PR64B PR64A PR63B PR63A RLM0_PLLCAP VCCPLL PR61B PR61A GNDIO3 PR60B Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RLM0_GDLLC_IN_A**/RDQ58 C (LVDS)* RLM0_GDLLC_FB_A/RDQ58 RLM0_GDLLT_FB_A/RDQ58 C T RLM0_GPLLC_FB_A/RDQ67 RLM0_GPLLT_FB_A/RDQ67 RLM0_GPLLC_IN_A**/RDQ67 RLM0_GPLLT_IN_A**/RDQ67 C T C (LVDS)* T (LVDS)* RDQ67 RDQ67 RDQ67 RDQ67 C T C (LVDS)* T (LVDS)* RDQ67 RDQ67 RDQS67 T C (LVDS)* T (LVDS)* RDQ67 RDQ67 RDQ67 RDQ67 T C (LVDS)* T (LVDS)* C DI/CSSPI0N DOUT/CSON BUSY/SISPI RDQ67 T C T C D4 D5 D6 D7 T C T C D1 D2 D3 C T C WRITEN CS1N CSN D0/SPIFASTN C T C T Dual Function Differential Ball/Pad Function CCLK INITN DONE GNDIO8 PR90B PR90A PR89B PR89A VCCIO8 PR88B PR88A PR87B GNDIO8 PR87A PR86B PR86A PR85B VCCIO8 PR85A PR84B PR84A PR83B GNDIO3 PR83A PR82B PR82A PR81B VCCIO3 PR81A PR80B PR80A GNDIO3 PR79B PR79A PR78B PR78A VCCIO3 PR77B PR77A PR76B PR76A RLM0_PLLCAP VCCPLL PR74B PR74A GNDIO3 PR73B Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RLM0_GDLLC_IN_A**/RDQ71 C (LVDS)* RLM0_GDLLC_FB_A/RDQ71 RLM0_GDLLT_FB_A/RDQ71 C T RLM0_GPLLC_FB_A/RDQ80 RLM0_GPLLT_FB_A/RDQ80 RLM0_GPLLC_IN_A**/RDQ80 RLM0_GPLLT_IN_A**/RDQ80 C T C (LVDS)* T (LVDS)* RDQ80 RDQ80 RDQ80 RDQ80 C T C (LVDS)* T (LVDS)* RDQ80 RDQ80 RDQS80 T C (LVDS)* T (LVDS)* RDQ80 RDQ80 RDQ80 RDQ80 T C (LVDS)* T (LVDS)* C DI/CSSPI0N DOUT/CSON BUSY/SISPI RDQ80 T C T C D4 D5 D6 D7 T C T C D1 D2 D3 C T C WRITEN CS1N CSN D0/SPIFASTN C T C T LFE2-70E/SE Dual Function Differential 4-98 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number T26 T20 T22 VCCIO R26 R25 R22 GND T21 P26 P25 R24 VCCIO R23 P20 R19 P21 GND P19 P23 P22 N22 VCCIO R21 N26 N25 GND N19 N20 M26 M25 VCCIO N18 N21 L26 L25 N24 M23 GND L21 K22 M24 N23 VCCIO K26 K25 M20 Ball/Pad Function PR60A PR59B PR59A VCCIO3 PR58B PR58A PR57B GNDIO3 PR57A PR56B PR56A PR55B VCCIO3 PR55A PR54B PR54A PR53B GNDIO3 PR53A PR52B PR52A PR51B VCCIO3 PR51A PR50B PR50A GNDIO3 PR49B PR49A PR48B PR48A VCCIO3 PR47B PR47A PR46B PR46A PR44B PR44A GNDIO2 PR43B PR43A PR42B PR42A VCCIO2 PR41B PR41A PR40B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 RDQ41 RDQS41 RDQ41 C (LVDS)* T (LVDS)* C RDQ41 RDQ41 RDQ41 RDQ41 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ50 VREF1_3/RDQ50 PCLKC3_0/RDQ50 PCLKT3_0/RDQ50 PCLKC2_0/RDQ41 PCLKT2_0/RDQ41 C T C (LVDS)* T (LVDS)* C T RDQ50 RDQ50 RDQ50 RDQ50 C T C (LVDS)* T (LVDS)* RDQ50 RDQ50 RDQS50 T C (LVDS)* T (LVDS)* RDQ50 RDQ50 RDQ50 RDQ50 T C (LVDS)* T (LVDS)* C RDQ58 RDQ58 RDQ58 RDQ50 T C (LVDS)* T (LVDS)* C RDQ58 RDQ58 RDQ58 RDQ58 T C (LVDS)* T (LVDS)* C RDQ58 RDQS58 RDQ58 C (LVDS)* T (LVDS)* C Dual Function RLM0_GDLLT_IN_A**/RDQ58 RDQ58 RDQ58 Differential T (LVDS)* C T Ball/Pad Function PR73A PR72B PR72A VCCIO3 PR71B PR71A PR70B GNDIO3 PR70A PR69B PR69A PR68B VCCIO3 PR68A PR67B PR67A PR66B GNDIO3 PR66A PR65B PR65A PR64B VCCIO3 PR64A PR63B PR63A GNDIO3 PR62B PR62A PR61B PR61A VCCIO3 PR60B PR60A PR59B PR59A PR57B PR57A GNDIO2 PR56B PR56A PR55B PR55A VCCIO2 PR54B PR54A PR53B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 RDQ54 RDQS54 RDQ54 C (LVDS)* T (LVDS)* C RDQ54 RDQ54 RDQ54 RDQ54 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ63 VREF1_3/RDQ63 PCLKC3_0/RDQ63 PCLKT3_0/RDQ63 PCLKC2_0/RDQ54 PCLKT2_0/RDQ54 C T C (LVDS)* T (LVDS)* C T RDQ63 RDQ63 RDQ63 RDQ63 C T C (LVDS)* T (LVDS)* RDQ63 RDQ63 RDQS63 T C (LVDS)* T (LVDS)* RDQ63 RDQ63 RDQ63 RDQ63 T C (LVDS)* T (LVDS)* C RDQ71 RDQ71 RDQ71 RDQ63 T C (LVDS)* T (LVDS)* C RDQ71 RDQ71 RDQ71 RDQ71 T C (LVDS)* T (LVDS)* C RDQ71 RDQS71 RDQ71 C (LVDS)* T (LVDS)* C LFE2-70E/SE Dual Function RLM0_GDLLT_IN_A**/RDQ71 RDQ71 RDQ71 Differential T (LVDS)* C T 4-99 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number GND M19 L22 M22 K21 VCCIO M21 K24 J24 GND VCCIO L20 GND J26 J25 J23 K23 VCCIO H26 H25 H24 GND H23 VCCIO G26 GND G25 F26 F25 K20 VCCIO L19 E26 E25 GND J22 H22 G24 G23 VCCIO K19 J19 D26 C26 F22 E24 GND Ball/Pad Function GNDIO2 PR40A PR39B PR39A PR38B VCCIO2 PR38A PR37B PR37A GNDIO2 VCCIO2 VCCPLL GNDIO2 PR26B PR26A PR25B PR25A VCCIO2 PR24B PR24A PR23B GNDIO2 PR23A VCCIO2 PR19B GNDIO2 PR19A PR18B PR18A PR17B VCCIO2 PR17A PR16B PR16A GNDIO2 PR15B PR15A PR14B PR14A VCCIO2 PR13B PR13A PR12B PR12A PR11B PR11A GNDIO2 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ16 RDQ16 RDQ16 RDQ16 RDQ8 RDQ8 C T C (LVDS)* T (LVDS)* C T RDQ16 RDQ16 RDQ16 RDQ16 C T C (LVDS)* T (LVDS)* RDQ16 RDQ16 RDQS16 T C (LVDS)* T (LVDS)* RDQ16 RDQ16 RDQ16 RDQ16 T C (LVDS)* T (LVDS)* C RDQ16 C RDQ24 T RDQ24 RDQS24*** RDQ24 C (LVDS)* T (LVDS)* C RUM0_SPLLC_FB_A/RDQ24 RUM0_SPLLT_FB_A/RDQ24 RUM0_SPLLC_IN_A/RDQ24 RUM0_SPLLT_IN_A/RDQ24 C T C T RDQ41 RDQ41 RDQ41 T C (LVDS)* T (LVDS)* RDQ41 RDQ41 RDQ41 RDQ41 T C (LVDS)* T (LVDS)* C Dual Function Differential Ball/Pad Function GNDIO2 PR53A PR52B PR52A PR51B VCCIO2 PR51A PR50B PR50A GNDIO2 VCCIO2 NC GNDIO2 PR39B PR39A PR38B PR38A VCCIO2 PR37B PR37A PR36B GNDIO2 PR36A VCCIO2 PR32B GNDIO2 PR32A PR31B PR31A PR30B VCCIO2 PR30A PR29B PR29A GNDIO2 PR28B PR28A PR27B PR27A VCCIO2 PR26B PR26A PR25B PR25A PR24B PR24A GNDIO2 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ29 RDQ29 RDQ29 RDQ29 RDQ21 RDQ21 C T C (LVDS)* T (LVDS)* C T RDQ29 RDQ29 RDQ29 RDQ29 C T C (LVDS)* T (LVDS)* RDQ29 RDQ29 RDQS29 T C (LVDS)* T (LVDS)* RDQ29 RDQ29 RDQ29 RDQ29 T C (LVDS)* T (LVDS)* C RDQ29 C RDQ37 T RDQ37 RDQS37*** RDQ37 C (LVDS)* T (LVDS)* C RUM0_SPLLC_FB_A/RDQ37 RUM0_SPLLT_FB_A/RDQ37 RUM0_SPLLC_IN_A/RDQ37 RUM0_SPLLT_IN_A/RDQ37 C T C T RDQ54 RDQ54 RDQ54 T C (LVDS)* T (LVDS)* RDQ54 RDQ54 RDQ54 RDQ54 T C (LVDS)* T (LVDS)* C LFE2-70E/SE Dual Function Differential 4-100 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number D25 C25 D24 B25 VCCIO H21 G22 B24 GND C24 D23 C23 G21 VCCIO H20 GND E22 F21 E23 GND D22 G20 J18 F20 VCCIO H19 A24 A23 E21 F19 C22 GND E20 B22 VCCIO B23 C20 D20 A22 A21 GND E19 C19 VCCIO B21 B20 D19 Ball/Pad Function PR10B PR10A PR9B PR9A VCCIO2 PR8B PR8A PR7B GNDIO2 PR7A PR6B PR6A PR5B VCCIO2 PR5A GNDIO2 PR2B PR2A PT82B GNDIO1 PT82A PT81B PT81A PT80B VCCIO1 PT80A PT79B PT79A PT78B PT78A PT77B GNDIO1 PT77A PT76B VCCIO1 PT76A PT75B PT75A PT74B PT74A GNDIO1 PT71B PT71A VCCIO1 PT70B PT70A PT69B Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C C T T C T C T T C T C T C T C VREF1_1 T C T C VREF2_2 VREF1_2 VREF2_1 C (LVDS)* T (LVDS)* C RDQ8 T RDQ8 RDQ8 RDQ8 RDQ8 T C (LVDS)* T (LVDS)* C RDQ8 RDQS8 RDQ8 C (LVDS)* T (LVDS)* C Dual Function RDQ8 RDQ8 RDQ8 RDQ8 Differential C (LVDS)* T (LVDS)* C T Ball/Pad Function PR23B PR23A PR22B PR22A VCCIO2 PR21B PR21A PR20B GNDIO2 PR20A PR19B PR19A PR18B VCCIO2 PR18A GNDIO2 PR2B PR2A PT100B GNDIO1 PT100A PT99B PT99A PT98B VCCIO1 PT98A PT97B PT97A PT96B PT96A PT95B GNDIO1 PT95A PT94B VCCIO1 PT94A PT93B PT93A PT92B PT92A GNDIO1 PT85B PT85A VCCIO1 PT79B PT79A PT78B Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C C T T C T C T T C T C T C T C VREF1_1 T C T C VREF2_2 VREF1_2 VREF2_1 C (LVDS)* T (LVDS)* C RDQ21 T RDQ21 RDQ21 RDQ21 RDQ21 T C (LVDS)* T (LVDS)* C RDQ21 RDQS21 RDQ21 C (LVDS)* T (LVDS)* C LFE2-70E/SE Dual Function RDQ21 RDQ21 RDQ21 RDQ21 Differential C (LVDS)* T (LVDS)* C T 4-101 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number B19 GND G17 E18 G19 F17 VCCIO A20 A19 E17 D18 B18 GND A18 E16 G16 F16 VCCIO H18 A17 B17 C18 B16 C17 GND D17 E15 VCCIO G15 A16 B15 D15 F15 A14 B14 GND C15 A15 A13 B13 VCCIO H17 H15 D13 C14 GND G14 Ball/Pad Function PT69A GNDIO1 PT68B PT68A PT67B PT67A VCCIO1 PT66B PT66A PT65B PT65A PT64B GNDIO1 PT64A PT63B PT63A PT62B VCCIO1 PT62A PT61B PT61A PT60B PT60A PT59B GNDIO1 PT59A PT58B VCCIO1 PT58A PT57B PT57A PT56B PT56A PT55B PT55A GNDIO1 PT54B PT54A PT53B PT53A VCCIO1 PT52B PT52A PT51B PT51A GNDIO1 PT50B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C T C T C T C T T C T C T C T T C T C T C T C T C T C C T C T C C T C T Dual Function Differential T Ball/Pad Function PT78A GNDIO1 PT77B PT77A PT76B PT76A VCCIO1 PT75B PT75A PT74B PT74A PT73B GNDIO1 PT73A PT72B PT72A PT71B VCCIO1 PT71A PT70B PT70A PT69B PT69A PT68B GNDIO1 PT68A PT67B VCCIO1 PT67A PT66B PT66A PT65B PT65A PT64B PT64A GNDIO1 PT63B PT63A PT62B PT62A VCCIO1 PT61B PT61A PT60B PT60A GNDIO1 PT59B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C T C T C T C T T C T C T C T T C T C T C T C T C T C C T C T C C T C T LFE2-70E/SE Dual Function Differential T 4-102 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number E14 A12 B12 VCCIO F14 D14 H16 H14 GND H13 A11 B11 C13 VCCIO E13 D12 F13 A10 B10 C12 GND C10 G13 VCCIO H12 A9 B9 E12 G12 A8 B8 GND E11 C9 A7 B7 VCCIO F12 D10 H11 G11 GND A6 B6 D8 C8 VCCIO Ball/Pad Function PT50A PT49B PT49A VCCIO1 PT48B PT48A XRES PT46B GNDIO0 PT46A PT45B PT45A PT44B VCCIO0 PT44A PT43B PT43A PT42B PT42A PT41B GNDIO0 PT41A PT40B VCCIO0 PT40A PT39B PT39A PT38B PT38A PT37B PT37A GNDIO0 PT36B PT36A PT35B PT35A VCCIO0 PT34B PT34A PT33B PT33A GNDIO0 PT32B PT32A PT31B PT31A VCCIO0 Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T T C T C T C T T C T C T C T C PCLKT0_0 T C T C PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T Dual Function Differential T C T Ball/Pad Function PT59A PT58B PT58A VCCIO1 PT57B PT57A XRES PT55B GNDIO0 PT55A PT54B PT54A PT53B VCCIO0 PT53A PT52B PT52A PT51B PT51A PT50B GNDIO0 PT50A PT49B VCCIO0 PT49A PT48B PT48A PT47B PT47A PT46B PT46A GNDIO0 PT45B PT45A PT44B PT44A VCCIO0 PT43B PT43A PT42B PT42A GNDIO0 PT41B PT41A PT40B PT40A VCCIO0 Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T T C T C T C T T C T C T C T C PCLKT0_0 T C T C PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T LFE2-70E/SE Dual Function Differential T C T 4-103 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number F11 E10 E9 D9 G10 GND H10 A5 B5 C7 VCCIO D7 E8 F10 F8 H9 C5 GND D5 B4 VCCIO GND VCCIO GND VCCIO C4 GND C3 A4 A3 B3 VCCIO B2 D4 D3 C2 C1 G8 GND G7 E7 VCCIO F7 E6 E5 G6 G5 Ball/Pad Function PT30B PT30A PT29B PT29A PT28B GNDIO0 PT28A PT27B PT27A PT26B VCCIO0 PT26A PT25B PT25A PT24B PT24A PT23B GNDIO0 PT23A PT22B VCCIO0 GNDIO0 VCCIO0 GNDIO0 VCCIO0 PT10B GNDIO0 PT10A PT9B PT9A PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A PT5B GNDIO0 PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 T C T C T T C T C T C T C T C T C C T T C T C T C T C T C Dual Function Differential C T C T C Ball/Pad Function PT39B PT39A PT38B PT38A PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A PT32B GNDIO0 PT32A PT31B VCCIO0 GNDIO0 VCCIO0 GNDIO0 VCCIO0 PT10B GNDIO0 PT10A PT9B PT9A PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A PT5B GNDIO0 PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 T C T C T T C T C T C T C T C T C C T T C T C T C T C T C LFE2-70E/SE Dual Function Differential C T C T C 4-104 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number L12 L13 L14 L15 M11 M12 M15 M16 N11 N16 P11 P16 R11 R12 R15 R16 T12 T13 T14 T15 D11 D6 G9 K12 J12 D16 D21 G18 J15 K15 F23 J20 L23 M17 M18 AA23 R17 R18 T23 V20 AC16 AC21 U15 V15 Y18 AC11 AC6 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 Bank 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 Dual Function Differential Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 Bank 0 0 0 0 0 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 5 5 LFE2-70E/SE Dual Function Differential 4-105 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number U12 V12 Y9 AA4 R10 R9 T4 V7 F4 J7 L4 M10 M9 AE25 V18 J10 J11 J16 J17 K18 K9 L18 L9 T18 T9 U18 U9 V10 V11 V16 V17 A2 A25 AA18 AA24 AA3 AA9 AD11 AD16 AD21 AD6 AE1 AE26 AF2 AF25 B1 B26 Ball/Pad Function VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 5 5 5 6 6 6 6 6 7 7 7 7 7 8 8 Dual Function Differential Ball/Pad Function VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 5 5 5 6 6 6 6 6 7 7 7 7 7 8 8 LFE2-70E/SE Dual Function Differential 4-106 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number C11 C16 C21 C6 F18 F24 F3 F9 J13 J14 J21 J6 K10 K11 K13 K14 K16 K17 L10 L11 L16 L17 L24 L3 M13 M14 N10 N12 N13 N14 N15 N17 P10 P12 P13 P14 P15 P17 R13 R14 T10 T11 T16 T17 T24 T3 U10 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LFE2-70E/SE Dual Function Differential 4-107 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA LFE2-50E/SE Ball Number U11 U13 U14 U16 U17 V13 V14 V21 V6 M3 N6 P24 Ball/Pad Function GND GND GND GND GND GND GND GND GND NC NC NC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND NC NC NC Bank LFE2-70E/SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-108 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA LFE2-70E/SE Ball Number VCCIO F4 F3 H4 G5 GND D2 D1 E2 VCCIO E1 GND VCCIO F1 F2 G1 G2 GND H8 H6 VCCIO G4 G3 H7 H5 GND H2 H1 J6 VCCIO J8 J2 J1 J5 GND J7 J4 J3 K6 K8 VCCIO K2 Ball/Pad Function VCCIO7 PL2A PL2B PL3A PL3B GNDIO7 PL4A PL4B PL5A VCCIO7 PL5B GNDIO7 VCCIO7 PL14A PL14B PL15A PL15B GNDIO7 PL18A PL18B VCCIO7 PL19A PL19B PL20A PL20B GNDIO7 PL21A PL21B PL22A VCCIO7 PL22B PL23A PL23B PL24A GNDIO7 PL24B PL25A PL25B PL26A PL26B VCCIO7 PL27A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ29 T (LVDS)* LDQ21 LDQ29 LDQ29 LDQ29 LDQ29 C T (LVDS)* C (LVDS)* T C LDQ21 LDQ21 LDQ21 LDQ21 C T (LVDS)* C (LVDS)* T LDQS21 LDQ21 LDQ21 T (LVDS)* C (LVDS)* T LDQ21 LDQ21 LDQ21 LDQ21 T (LVDS)* C (LVDS)* T C LDQ21 LDQ21 T C LUM1_SPLLT_IN_A/LDQ12 LUM1_SPLLC_IN_A/LDQ12 LUM1_SPLLT_FB_A/LDQ12 LUM1_SPLLC_FB_A/LDQ12 T (LVDS)* C (LVDS)* T C C T (LVDS)* C (LVDS)* T VREF2_7 VREF1_7 T (LVDS)* C (LVDS)* T C Dual Function Differential 4-109 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number K1 K5 K7 GND K4 K3 L8 VCCIO L6 L2 L1 L7 GND L5 L4 L3 M8 M6 VCCIO M2 M1 M7 M5 GND M4 M3 N6 VCCIO N8 N5 N7 GND VCCIO T9 R9 P7 VCCIO N2 N1 P6 P5 GND P4 Ball/Pad Function PL27B PL28A PL28B GNDIO7 PL29A PL29B PL30A VCCIO7 PL30B PL31A PL31B PL32A GNDIO7 PL32B PL33A PL33B PL34A PL34B VCCIO7 PL35A PL35B PL36A PL36B GNDIO7 PL37A PL37B PL38A VCCIO7 PL38B PL39A PL39B GNDIO7 VCCIO7 PL50A PL51A PL51B VCCIO7 PL52A PL52B PL53A PL53B GNDIO7 PL54A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQS54 T (LVDS)* LDQ54 LDQ54 LDQ54 LDQ54 T (LVDS)* C (LVDS)* T C LDQ54 LDQ54 LDQ54 T C LUM0_SPLLC_IN_A/LDQ37 LUM0_SPLLT_FB_A/LDQ37 LUM0_SPLLC_FB_A/LDQ37 C T C LDQS37 LDQ37 LUM0_SPLLT_IN_A/LDQ37 T (LVDS)* C (LVDS)* T LDQ37 LDQ37 LDQ37 LDQ37 T (LVDS)* C (LVDS)* T C LDQ29 LDQ37 LDQ37 LDQ37 LDQ37 C T (LVDS)* C (LVDS)* T C LDQ29 LDQ29 LDQ29 LDQ29 C T (LVDS)* C (LVDS)* T LDQS29 LDQ29 LDQ29 T (LVDS)* C (LVDS)* T Dual Function LDQ29 LDQ29 LDQ29 Differential C (LVDS)* T C 4-110 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number P3 R6 VCCIO R8 P2 P1 R5 GND R7 R4 R3 T5 T7 T3 VCCIO T4 T6 T8 T2 GND T1 U7 U5 VCCIO U4 U3 U8 U6 GND U2 U1 V7 V5 VCCIO V2 V1 V8 V6 GND W1 W2 W5 VCCIO Ball/Pad Function PL54B PL55A VCCIO7 PL55B PL56A PL56B PL57A GNDIO7 PL57B PL59A PL59B PL60A PL60B PL61A VCCIO6 PL61B PL62A PL62B PL63A GNDIO6 PL63B PL64A PL64B VCCIO6 PL65A PL65B PL66A PL66B GNDIO6 PL67A PL67B PL68A PL68B VCCIO6 PL69A PL69B PL70A PL70B GNDIO6 PL71A PL71B PL72A VCCIO6 Bank 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQS71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T LDQ71 LDQ71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T C LDQ71 LDQ71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T C LDQ63 LDQ63 LDQ63 LDQ63 T (LVDS)* C (LVDS)* T C LDQ63 LDQ63 LDQ63 C (LVDS)* T C LDQ63 LDQ63 LDQ63 LDQS63 C (LVDS)* T C T (LVDS)* PCLKC7_0/LDQ54 PCLKT6_0/LDQ63 PCLKC6_0/LDQ63 VREF2_6/LDQ63 VREF1_6/LDQ63 LDQ63 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ54 LDQ54 LDQ54 PCLKT7_0/LDQ54 C T (LVDS)* C (LVDS)* T Dual Function LDQ54 LDQ54 Differential C (LVDS)* T 4-111 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number W7 W4 W3 W6 GND W8 Y8 Y1 Y2 Y5 Y6 Y4 VCCIO Y3 AA6 AA8 AA2 GND AA1 AA7 AA5 VCCIO AA4 AA3 AB7 AB5 GND AB2 AB1 AB8 AB6 VCCIO AB4 AB3 AC7 AC5 GND AC2 AC1 AC6 VCCIO AD6 AD1 Ball/Pad Function PL72B PL73A PL73B PL74A GNDIO6 PL74B LLM0_PLLCAP PL76A PL76B PL77A PL77B PL78A VCCIO6 PL78B PL79A PL79B PL80A GNDIO6 PL80B PL81A PL81B VCCIO6 PL82A PL82B PL83A PL83B GNDIO6 PL84A PL84B PL85A PL85B VCCIO6 PL86A PL86B PL87A PL87B GNDIO6 PL88A PL88B PL89A VCCIO6 PL89B PL90A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ88 LDQ88 C T (LVDS)* LDQS88 LDQ88 LDQ88 T (LVDS)* C (LVDS)* T LDQ88 LDQ88 LDQ88 LDQ88 T (LVDS)* C (LVDS)* T C LDQ88 LDQ88 LDQ88 LDQ88 T (LVDS)* C (LVDS)* T C LDQ80 LDQ80 LDQ80 LDQ80 T (LVDS)* C (LVDS)* T C LDQ80 LDQ80 LDQ80 C (LVDS)* T C LDQ80 LDQ80 LDQ80 LDQS80 C (LVDS)* T C T (LVDS)* LLM0_GPLLT_IN_A**/LDQ80 LLM0_GPLLC_IN_A**/LDQ80 LLM0_GPLLT_FB_A/LDQ80 LLM0_GPLLC_FB_A/LDQ80 LDQ80 T (LVDS)* C (LVDS)* T C T (LVDS)* LLM0_GDLLC_FB_D/LDQ71 C Dual Function LDQ71 LLM0_GDLLT_IN_A**/LDQ71 LLM0_GDLLC_IN_A**/LDQ71 LLM0_GDLLT_FB_A/LDQ71 Differential C T (LVDS)* C (LVDS)* T 4-112 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number AD2 AD7 GND AB9 AD5 AE7 AD4 AA9 AD3 AC8 AE8 AD8 AF8 AG7 VCCIO AH7 AC9 AE9 AD9 GND AF9 AB10 AA10 AJ7 VCCIO AK7 AC10 AE10 AJ8 GND AK8 AF6 AF7 AG5 AH5 AG6 AH6 VCCIO AJ4 AK4 GND AJ5 AK5 Ball/Pad Function PL90B PL91A GNDIO6 PL91B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A VCCIO5 PB4B PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A VCCIO5 PB8B PB9A PB9B PB10A GNDIO5 PB10B PB11A PB11B PB12A PB12B PB13A PB13B VCCIO5 PB14A PB14B GNDIO5 PB15A PB15B Bank 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQS15 BDQ15 T C BDQ15 BDQ15 T C BDQ6 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 C T C T C T C BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQS6 C T C T VREF2_5/BDQ6 VREF1_5/BDQ6 BDQ6 BDQ6 BDQ6 T C T C T LDQ88 C Dual Function LDQ88 LDQ88 Differential C (LVDS)* T 4-113 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number AJ6 AK6 VCCIO GND AD10 AF10 AC11 AD11 AG9 AH9 VCCIO AE11 AG10 GND AJ9 AK9 AF11 AH10 AC12 AE12 VCCIO AD12 AF12 AJ10 AK10 GND AG11 AH11 AE13 AC13 AF13 VCCIO AD13 AJ11 AK11 AD14 GND AC14 AG12 AE14 AJ12 VCCIO AK12 Ball/Pad Function PB16A PB16B VCCIO5 GNDIO5 PB29A PB29B PB30A PB30B PB31A PB31B VCCIO5 PB32A PB32B GNDIO5 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO5 PB36A PB36B PB37A PB37B GNDIO5 PB38A PB38B PB39A PB39B PB40A VCCIO5 PB40B PB41A PB41B PB42A GNDIO5 PB42B PB43A PB43B PB44A VCCIO5 PB44B Bank 5 5 5 5 5 5 5 5 5 99 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ42 C BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 BDQ42 BDQS42 C T C T BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 T C T C T BDQ33 BDQ33 BDQ33 BDQ33 T C T C BDQS33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C BDQ33 BDQ33 T C BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C Dual Function BDQ15 BDQ15 Differential T C 4-114 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number AH12 AF14 AJ13 GND AK13 AB15 AD15 AE15 AF15 AG15 AG14 VCCIO AH15 AH14 GND AJ14 AK14 AD16 AF16 AJ15 AK15 VCCIO GND AE16 VCCIO AC15 AJ16 AK16 AC16 GND AB16 AH17 AG17 AF17 VCCIO AD17 AE17 AC17 AJ17 GND AK17 AK18 AJ18 Ball/Pad Function PB45A PB45B PB46A GNDIO5 PB46B PB47A PB47B PB48A PB48B PB49A PB49B VCCIO5 PB50A PB50B GNDIO5 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO5 GNDIO5 PB58A VCCIO4 PB58B PB59A PB59B PB60A GNDIO4 PB60B PB61A PB61B PB62A VCCIO4 PB62B PB63A PB63B PB64A GNDIO4 PB64B PB65A PB65B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ60 BDQ69 BDQ69 C T C BDQ60 BDQ60 BDQ60 BDQ60 C T C T BDQ60 BDQ60 BDQ60 BDQ60 C T C T PCLKC4_0/BDQ60 BDQ60 BDQ60 BDQS60 C T C T PCLKT4_0/BDQ60 T BDQS51 BDQ51 BDQ51 BDQ51 PCLKT5_0/BDQ51 PCLKC5_0/BDQ51 T C T C T C BDQ51 BDQ51 T C BDQ42 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 C T C T C T C Dual Function BDQ42 BDQ42 BDQ42 Differential T C T 4-115 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number AD18 AF18 AC18 AE18 VCCIO AG19 AH19 GND AE19 AF19 AC19 AD19 AJ19 AK19 VCCIO AF20 AH20 AE20 AG20 GND AD20 AC20 AH21 AF21 AJ20 VCCIO AK20 AG21 AE21 AD21 GND AC21 AD22 AB21 AJ21 VCCIO AK21 GND VCCIO AJ25 AK24 AJ24 AK25 Ball/Pad Function PB66A PB66B PB67A PB67B VCCIO4 PB68A PB68B GNDIO4 PB69A PB69B PB70A PB70B PB71A PB71B VCCIO4 PB72A PB72B PB73A PB73B GNDIO4 PB74A PB74B PB75A PB75B PB76A VCCIO4 PB76B PB77A PB77B PB78A GNDIO4 PB78B PB79A PB79B PB80A VCCIO4 PB80B GNDIO4 VCCIO4 PB87A PB87B PB88A PB88B Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQS87*** BDQ87 BDQ87 BDQ87 T C T C BDQ78 C BDQ78 BDQ78 BDQ78 BDQ78 C T C T BDQ78 BDQ78 BDQ78 BDQS78 C T C T BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T BDQ69 BDQ69 BDQ69 BDQ69 T C T C BDQS69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ69 BDQ69 T C Dual Function BDQ69 BDQ69 BDQ69 BDQ69 Differential T C T C 4-116 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number AH24 AH25 VCCIO AJ26 AK26 AF25 AG25 GND AK22 AJ22 AE22 AF22 AG22 VCCIO AH22 AG24 AG23 AE23 GND AC22 AJ23 VCCIO AK23 AD24 AF24 AC23 GND AE24 AE25 AB22 AE26 AA22 AD25 AD26 AC24 GND AC25 AE27 AC26 AE28 VCCIO AD27 AD28 Ball/Pad Function PB89A PB89B VCCIO4 PB90A PB90B PB91A PB91B GNDIO4 PB92A PB92B PB93A PB93B PB94A VCCIO4 PB94B PB95A PB95B PB96A GNDIO4 PB97A PB98A VCCIO4 PB98B PB99A PB99B PB100A GNDIO4 PB100B CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO4 PR90B PR90A PR89B PR89A VCCIO8 PR88B PR88A Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 D1 D2 C T WRITEN CS1N CSN D0/SPIFASTN C T C T VREF1_4/BDQ96 C BDQ96 BDQ96 BDQ96 VREF2_4/BDQ96 C T C T BDQ96 BDQ96 T BDQ96 BDQ96 BDQ96 BDQS96 C T C BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 T C T C T BDQ87 BDQ87 BDQ87 BDQ87 T C T C Dual Function BDQ87 BDQ87 Differential T C 4-117 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number AB24 GND AB23 AB25 AB26 AC27 VCCIO AB27 AD29 AD30 AA25 GND AA23 AC29 AC30 AA26 VCCIO AA24 AB29 AB30 GND Y23 Y25 AA27 AA28 VCCIO Y24 Y26 AA29 AA30 R22 W23 W25 GND Y27 Y28 W24 W26 VCCIO Y29 Y30 V25 GND Ball/Pad Function PR87B GNDIO4 PR87A PR86B PR86A PR85B VCCIO8 PR85A PR84B PR84A PR83B GNDIO3 PR83A PR82B PR82A PR81B VCCIO3 PR81A PR80B PR80A GNDIO3 PR79B PR79A PR78B PR78A VCCIO3 PR77B PR77A PR76B PR76A RLM0_PLLCAP PR74B PR74A GNDIO3 PR73B PR73A PR72B PR72A VCCIO3 PR71B PR71A PR70B GNDIO3 Bank 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ71 RDQS71 RDQ71 C (LVDS)* T (LVDS)* C RLM0_GDLLC_IN_A**/RDQ71 RLM0_GDLLT_IN_A**/RDQ71 RDQ71 RDQ71 C (LVDS)* T (LVDS)* C T RLM0_GDLLC_FB_A/RDQ71 RLM0_GDLLT_FB_A/RDQ71 C T RLM0_GPLLC_FB_A/RDQ80 RLM0_GPLLT_FB_A/RDQ80 RLM0_GPLLC_IN_A**/RDQ80 RLM0_GPLLT_IN_A**/RDQ80 C T C (LVDS)* T (LVDS)* RDQ80 RDQ80 RDQ80 RDQ80 C T C (LVDS)* T (LVDS)* RDQ80 RDQ80 RDQS80 T C (LVDS)* T (LVDS)* RDQ80 RDQ80 RDQ80 RDQ80 T C (LVDS)* T (LVDS)* C DI/CSSPI0N DOUT/CSON BUSY/SISPI RDQ80 T C T C D4 D5 D6 D7 T C T C Dual Function D3 Differential C 4-118 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number V23 W27 W28 V26 VCCIO V24 W29 W30 U25 GND U23 V29 V30 U26 VCCIO U24 U27 U28 GND T23 T25 U29 U30 VCCIO T24 T26 T27 T28 R24 R26 GND T29 T30 R23 R25 VCCIO R27 R28 P26 GND P24 R29 R30 Ball/Pad Function PR70A PR69B PR69A PR68B VCCIO3 PR68A PR67B PR67A PR66B GNDIO3 PR66A PR65B PR65A PR64B VCCIO3 PR64A PR63B PR63A GNDIO3 PR62B PR62A PR61B PR61A VCCIO3 PR60B PR60A PR59B PR59A PR57B PR57A GNDIO2 PR56B PR56A PR55B PR55A VCCIO2 PR54B PR54A PR53B GNDIO2 PR53A PR52B PR52A Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ54 RDQ54 RDQ54 T C (LVDS)* T (LVDS)* RDQ54 RDQS54 RDQ54 C (LVDS)* T (LVDS)* C RDQ54 RDQ54 RDQ54 RDQ54 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ63 VREF1_3/RDQ63 PCLKC3_0/RDQ63 PCLKT3_0/RDQ63 PCLKC2_0/RDQ54 PCLKT2_0/RDQ54 C T C (LVDS)* T (LVDS)* C T RDQ63 RDQ63 RDQ63 RDQ63 C T C (LVDS)* T (LVDS)* RDQ63 RDQ63 RDQS63 T C (LVDS)* T (LVDS)* RDQ63 RDQ63 RDQ63 RDQ63 T C (LVDS)* T (LVDS)* C RDQ71 RDQ71 RDQ71 RDQ63 T C (LVDS)* T (LVDS)* C Dual Function RDQ71 RDQ71 RDQ71 RDQ71 Differential T C (LVDS)* T (LVDS)* C 4-119 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number P25 VCCIO P23 P27 P28 GND VCCIO N24 N26 N23 N25 VCCIO P29 P30 M26 GND M24 N29 N30 M25 VCCIO M23 M27 M28 L26 GND L24 M29 M30 L25 VCCIO L23 L27 L28 GND K24 K26 L29 L30 VCCIO K23 K25 K27 Ball/Pad Function PR51B VCCIO2 PR51A PR50B PR50A GNDIO2 VCCIO2 PR39B PR39A PR38B PR38A VCCIO2 PR37B PR37A PR36B GNDIO2 PR36A PR35B PR35A PR34B VCCIO2 PR34A PR33B PR33A PR32B GNDIO2 PR32A PR31B PR31A PR30B VCCIO2 PR30A PR29B PR29A GNDIO2 PR28B PR28A PR27B PR27A VCCIO2 PR26B PR26A PR25B Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ29 RDQ29 RDQ29 C T C (LVDS)* RDQ29 RDQ29 RDQ29 RDQ29 C T C (LVDS)* T (LVDS)* RDQ29 RDQ29 RDQS29 T C (LVDS)* T (LVDS)* RDQ29 RDQ29 RDQ29 RDQ29 T C (LVDS)* T (LVDS)* C RDQ37 RDQ37 RDQ37 RDQ29 T C (LVDS)* T (LVDS)* C RDQ37 RDQ37 RDQ37 RDQ37 T C (LVDS)* T (LVDS)* C RDQ37 RDQS37 RDQ37 C (LVDS)* T (LVDS)* C RUM0_SPLLC_FB_A/RDQ37 RUM0_SPLLT_FB_A/RDQ37 RUM0_SPLLC_IN_A/RDQ37 RUM0_SPLLT_IN_A/RDQ37 C T C T RDQ54 RDQ54 RDQ54 T C (LVDS)* T (LVDS)* Dual Function RDQ54 Differential C 4-120 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number K28 J24 J26 GND K29 K30 J23 J25 VCCIO J27 J28 H26 GND H24 J29 J30 H25 VCCIO H23 G27 GND H27 G29 G28 VCCIO GND G26 G25 G30 F30 VCCIO F26 F27 F29 GND F28 H29 H30 VCCIO B26 A26 GND C25 Ball/Pad Function PR25A PR24B PR24A GNDIO2 PR23B PR23A PR22B PR22A VCCIO2 PR21B PR21A PR20B GNDIO2 PR20A PR19B PR19A PR18B VCCIO2 PR18A PR15B GNDIO2 PR15A PR14B PR14A VCCIO2 GNDIO2 PR6B PR6A PR5B PR5A VCCIO2 PR4B PR4A PR3B GNDIO2 PR3A PR2B PR2A VCCIO2 PT100B PT100A GNDIO1 PT99B Bank 2 2 2 2 2 2 2 99 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 C VREF2_1 VREF1_1 C T VREF2_2 VREF1_2 T C (LVDS)* T (LVDS)* C (LVDS)* T (LVDS)* C C (LVDS)* T (LVDS)* C T RUM1_SPLLT_FB_A/RDQ12 RUM1_SPLLC_IN_A/RDQ12 RUM1_SPLLT_IN_A/RDQ12 T C (LVDS)* T (LVDS)* RDQ21 RUM1_SPLLC_FB_A/RDQ12 T C RDQ21 RDQ21 RDQ21 RDQ21 T C (LVDS)* T (LVDS)* C RDQ21 RDQS21 RDQ21 C (LVDS)* T (LVDS)* C RDQ21 RDQ21 RDQ21 RDQ21 C (LVDS)* T (LVDS)* C T Dual Function RDQ29 RDQ21 RDQ21 Differential T (LVDS)* C T 4-121 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number D25 J22 J21 VCCIO B25 A25 E24 F24 GND F23 H22 D24 C24 VCCIO E23 G23 B24 A24 C27 GND D27 C26 D26 A27 VCCIO B27 A28 B28 A29 B29 GND VCCIO H21 F22 VCCIO B23 A23 G24 E22 GND D22 C22 G22 Ball/Pad Function PT99A PT98B PT98A VCCIO1 PT97B PT97A PT96B PT96A GNDIO1 PT95B PT95A PT94B PT94A VCCIO1 PT93B PT93A PT92B PT92A PT91B GNDIO1 PT91A PT90B PT90A PT89B VCCIO1 PT89A PT88B PT88A PT87B PT87A GNDIO1 VCCIO1 PT80B PT80A VCCIO1 PT79B PT79A PT78B PT78A GNDIO1 PT77B PT77A PT76B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C C T C T C T T C T C T T C T C C T C T C C T C T C T C T Dual Function Differential T C T 4-122 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number E21 VCCIO B22 A22 H20 F21 F20 GND H19 D21 C21 E20 VCCIO G21 B21 A21 F19 G20 E19 GND G19 D20 VCCIO C20 B20 A20 F18 H18 D19 C19 GND G18 E18 H17 F17 VCCIO G17 E17 B19 A19 GND D17 B18 Ball/Pad Function PT76A VCCIO1 PT75B PT75A PT74B PT74A PT73B GNDIO1 PT73A PT72B PT72A PT71B VCCIO1 PT71A PT70B PT70A PT69B PT69A PT68B GNDIO1 PT68A PT67B VCCIO1 PT67A PT66B PT66A PT65B PT65A PT64B PT64A GNDIO1 PT63B PT63A PT62B PT62A VCCIO1 PT61B PT61A PT60B PT60A GNDIO1 PT59B PT59A Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C T T C T C T C T T C T C T C T C T C T C C T C T C Dual Function Differential T 4-123 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number C17 A18 VCCIO H16 F16 K16 E16 GND G16 B17 A17 J15 VCCIO J16 C16 D16 F15 H15 E15 GND G15 C15 VCCIO D15 B16 A16 E14 G14 B15 A15 GND H14 F14 D14 C14 VCCIO G13 E13 B14 A14 GND H13 F13 Ball/Pad Function PT58B PT58A VCCIO1 PT57B PT57A XRES PT55B GNDIO0 PT55A PT54B PT54A PT53B VCCIO0 PT53A PT52B PT52A PT51B PT51A PT50B GNDIO0 PT50A PT49B VCCIO0 PT49A PT48B PT48A PT47B PT47A PT46B PT46A GNDIO0 PT45B PT45A PT44B PT44A VCCIO0 PT43B PT43A PT42B PT42A GNDIO0 PT41B PT41A Bank 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T T C T C T C T T C T C T C T C PCLKT0_0 T C T C PCLKC0_0 C PCLKC1_0 PCLKT1_0 C T Dual Function Differential C T 4-124 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number G12 E12 VCCIO B13 A13 H12 F12 C12 GND D12 B12 A12 E11 VCCIO G11 F11 H11 C11 D11 B11 GND A11 E10 VCCIO G10 F10 H10 D10 C10 GND VCCIO A7 B7 A6 B6 C7 GND D7 D8 VCCIO E7 C6 D6 Ball/Pad Function PT40B PT40A VCCIO0 PT39B PT39A PT38B PT38A PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A PT32B GNDIO0 PT32A PT31B VCCIO0 PT31A PT30B PT30A PT29B PT29A GNDIO0 VCCIO0 PT16B PT16A PT15B PT15A PT14B GNDIO0 PT14A PT13B VCCIO0 PT13A PT12B PT12A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T T C C T C T C T C T C T T C T C T C T C T C T C C T C T C Dual Function Differential C T 4-125 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number C5 D5 E9 G9 GND B10 A10 D9 C9 VCCIO F9 H9 B9 A9 GND E8 G8 A8 B8 VCCIO F8 F7 J10 J9 AA11 AA20 K11 K21 K22 L11 L12 L13 L18 L19 L20 M11 M20 N11 N20 V11 V20 W11 W20 Ball/Pad Function PT11B PT11A PT10B PT10A GNDIO0 PT9B PT9A PT8B PT8A VCCIO0 PT7B PT7A PT6B PT6A GNDIO0 PT5B PT5A PT4B PT4A VCCIO0 PT3B PT3A PT2B PT2A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF2_0 VREF1_0 C T C T C T C T C T C T C T C T Dual Function Differential C T C T 4-126 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number Y10 Y11 Y12 Y13 Y18 Y19 Y20 J13 J14 K12 K13 K14 K15 J17 J18 J20 K17 K18 K20 L21 M21 M22 N21 N22 R21 U21 U22 V21 V22 W21 Y22 AA16 AA17 AA18 AA19 AB17 AB18 AA12 AA13 AA14 AB12 AB13 AB14 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 Bank 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 Dual Function Differential 4-127 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number U10 U9 V10 W10 W9 Y9 L10 L9 M10 N10 P10 R10 AA21 Y21 AA15 AB11 AB19 AB20 J11 J12 J19 K19 L22 M9 N9 P21 P9 T10 T21 V9 W22 A1 A30 AC28 AC3 AH13 AH18 AH23 AH28 AH3 AH8 AK1 AK30 Ball/Pad Function VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND Bank 6 6 6 6 6 6 7 7 7 7 7 7 8 8 Dual Function Differential 4-128 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number C13 C18 C23 C28 C3 C8 H28 H3 L14 L15 L16 L17 M12 M13 M14 M15 M16 M17 M18 M19 N12 N13 N14 N15 N16 N17 N18 N19 N28 N3 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 R11 R12 R13 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential 4-129 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number R14 R15 R16 R17 R18 R19 R20 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V12 V13 V14 V15 V16 V17 V18 V19 V28 V3 W12 W13 W14 W15 W16 W17 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential 4-130 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number W18 W19 Y14 Y15 Y16 Y17 A2 A3 A4 A5 AB28 AC4 AD23 AE1 AE2 AE29 AE3 AE30 AE4 AE5 AE6 AF1 AF2 AF23 AF26 AF27 AF28 AF29 AF3 AF30 AF4 AF5 AG1 AG13 AG16 AG18 AG2 AG26 AG27 AG28 AG29 AG3 AG30 Ball/Pad Function GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential 4-131 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number AG4 AG8 AH1 AH16 AH2 AH26 AH27 AH29 AH30 AH4 AJ1 AJ2 AJ27 AJ28 AJ29 AJ3 AJ30 AK2 AK27 AK28 AK29 AK3 B1 B2 B3 B30 B4 B5 C1 C2 C29 C30 C4 D13 D18 D23 D28 D29 D3 D30 D4 E25 E26 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential 4-132 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2-70E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2-70E/SE Ball Number E27 E28 E29 E3 E30 E4 E5 E6 F25 F5 F6 G6 G7 K10 K9 N27 N4 R1 R2 V27 V4 P22 P8 T22 Y7 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCPLL VCCPLL VCCPLL VCCPLL Bank Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-133 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE Ball Number A2 B2 D3 C2 E4 VCCIO E5 B1 C1 D2 GNDIO D1 E1 F1 VCCIO F3 F2 F6 F5 GNDIO G4 G3 G1 G2 H1 VCCIO J1 H2 H3 GNDIO VCCIO G6 H6 J2 GNDIO K1 H4 H5 J4 K4 VCCIO J6 GNDIO J5 K3 K2 VCCIO GNDIO L1 Ball/Pad Function PL2A PL2B PL3A PL3B PL4A VCCIO7 PL4B PL5A PL5B PL6A GNDIO7 PL6B PL7A PL7B VCCIO7 PL8A PL8B PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B PL13A VCCIO7 PL13B PL14A PL14B GNDIO7 VCCIO7 PL24A PL24B PL25A GNDIO7 PL25B PL27A PL27B PL28A PL28B VCCIO6 PL31A GNDIO6 PL31B PL32A PL32B VCCIO6 GNDIO6 PL42A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 LLM0_GPLLT_IN_A T (LVDS)* LLM1_SPLLC_IN_A LLM1_SPLLT_FB_A LLM1_SPLLC_FB_A C (LVDS)* T C LLM1_SPLLT_IN_A T (LVDS)* PCLKC7_0/LDQ22 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T (LVDS)* C (LVDS)* T C LDQ22 LDQ22 PCLKT7_0/LDQ22 T (LVDS)* C (LVDS)* T C (LVDS)* T C LUM0_SPLLT_IN_A LUM0_SPLLC_IN_A LUM0_SPLLT_FB_A LUM0_SPLLC_FB_A T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ6 LDQ6 VREF2_7/LDQ6 VREF1_7/LDQ6 T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 LDQ6 C (LVDS)* T C LDQ6 LDQ6 LDQ6 LDQS6 C (LVDS)* T C T (LVDS)* Dual Function LDQ6 LDQ6 LDQ6 LDQ6 LDQ6 Differential T (LVDS)* C (LVDS)* T C T (LVDS)* Ball/Pad Function PL2A PL2B PL3A PL3B PL4A VCCIO7 PL4B PL5A PL5B PL6A GNDIO7 PL6B PL7A PL7B VCCIO7 PL8A PL8B PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B PL13A VCCIO7 PL13B PL14A PL14B GNDIO7 VCCIO7 PL34A PL34B PL35A GNDIO7 PL35B PL37A PL37B PL38A PL38B VCCIO6 PL41A GNDIO6 PL41B PL42A PL42B VCCIO6 GNDIO6 PL57A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 LLM0_GPLLT_IN_A**/LDQS57*** T (LVDS)* LLM2_SPLLC_IN_A LLM2_SPLLT_FB_A LLM2_SPLLC_FB_A C(LVDS)* T C LLM2_SPLLT_IN_A T (LVDS)* PCLKC7_0/LDQ32 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T (LVDS)* C(LVDS)* T C LDQ32 LDQ32 PCLKT7_0/LDQ32 T (LVDS)* C(LVDS)* T LDQ15 LDQ15 LDQ15 C(LVDS)* T C LUM0_SPLLT_IN_A/LDQ15 LUM0_SPLLC_IN_A/LDQ15 LUM0_SPLLT_FB_A/LDQ15 LUM0_SPLLC_FB_A/LDQ15 LDQ15 T (LVDS)* C(LVDS)* T C T (LVDS)* LDQ6 LDQ6 VREF2_7/LDQ6 VREF1_7/LDQ6 T (LVDS)* C(LVDS)* T C LDQ6 LDQ6 LDQ6 C(LVDS)* T C LDQ6 LDQ6 LDQ6 LDQS6 C(LVDS)* T C T (LVDS)* LFE2M35E/SE Dual Function LDQ6 LDQ6 LDQ6 LDQ6 LDQ6 Differential T (LVDS)* C(LVDS)* T C T (LVDS)* 4-134 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE Ball Number GNDIO L2 L3 L4 VCCIO M1 N1 N2 N3 GNDIO M4 VCCIO GNDIO K6 L5 N4 N6 K7 M5 N5 L6 M6 P3 VCCIO P4 P2 P1 R1 GNDIO R2 R3 T2 R4 VCCIO T3 T4 GNDIO T5 VCCIO GNDIO T6 R6 P6 P7 VCCIO GNDIO T7 VCCIO T8 Ball/Pad Function GNDIO6 PL42B PL43A PL43B VCCIO6 PL44A PL44B PL45A PL45B GNDIO6 LLM0_PLLCAP VCCIO6 GNDIO6 TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A VCCIO5 PB4B PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A VCCIO5 PB8B PB10A GNDIO5 PB10B VCCIO5 GNDIO5 PB16A PB16B PB17A PB17B VCCIO5 GNDIO5 PB22A VCCIO4 PB22B Bank 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 PCLKC4_0/BDQ24 C PCLKT4_0/BDQ24 T VREF2_5/BDQ15 VREF1_5/BDQ15 PCLKT5_0/BDQ15 PCLKC5_0/BDQ15 T C T C BDQ6 C BDQ6 BDQ6 C T BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQS6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T LLM0_GDLLT_IN_A LLM0_GDLLC_IN_A LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A LLM0_GPLLT_FB_A LLM0_GPLLC_FB_A C (LVDS)* T C Dual Function Differential Ball/Pad Function GNDIO6 PL57B PL58A PL58B VCCIO6 PL59A PL59B PL60A PL60B GNDIO6 LLM0_PLLCAP VCCIO6 GNDIO6 TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A VCCIO5 PB4B PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A VCCIO5 PB8B PB10A GNDIO5 PB10B VCCIO5 GNDIO5 PB34A PB34B PB35A PB35B VCCIO5 GNDIO5 PB40A VCCIO4 PB40B Bank 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 PCLKC4_0/BDQ42 C PCLKT4_0/BDQ42 T VREF2_5/BDQ33 VREF1_5/BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 T C T C BDQ6 C BDQ6 BDQ6 C T BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQS6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T LLM0_GDLLT_IN_A**/LDQ57 LLM0_GDLLC_IN_A**/LDQ57 LLM0_GDLLT_FB_A/LDQ57 LLM0_GDLLC_FB_A/LDQ57 T (LVDS)* C(LVDS)* T C LLM0_GPLLC_IN_A**/LDQ57 LLM0_GPLLT_FB_A/LDQ57 LLM0_GPLLC_FB_A/LDQ57 C(LVDS)* T C LFE2M35E/SE Dual Function Differential 4-135 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE Ball Number L7 L8 GNDIO VCCIO GNDIO P8 N8 R7 R8 N7 M8 VCCIO R9 T9 GNDIO T10 R10 N9 P10 VCCIO GNDIO L9 M9 T11 R11 VCCIO T12 T13 GNDIO P11 N10 T14 R13 R15 R16 VCCIO R14 P15 P16 P14 GNDIO L11 L10 P13 N12 N11 M11 N13 GNDIO Ball/Pad Function PB23A PB23B GNDIO4 VCCIO4 GNDIO4 PB29A PB29B PB30A PB30B PB31A PB31B VCCIO4 PB32A PB32B GNDIO4 PB33A PB33B PB34A PB34B VCCIO4 GNDIO4 PB47A PB47B PB49A PB49B VCCIO4 PB50A PB50B GNDIO4 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO4 PB54A PB54B PB55A PB55B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 BDQ51 BDQ51 BDQ51 BDQ51 T C T C BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ51 BDQ51 T C BDQ51 BDQ51 BDQ51 BDQ51 T C T C BDQS33 BDQ33 BDQ33 BDQ33 T C T C BDQ33 BDQ33 T C BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C Dual Function VREF2_4/BDQ24 VREF1_4/BDQ24 Differential T C Ball/Pad Function PB41A PB41B GNDIO4 VCCIO4 GNDIO4 PB47A PB47B PB48A PB48B PB49A PB49B VCCIO4 PB50A PB50B GNDIO4 PB51A PB51B PB52A PB52B VCCIO4 GNDIO4 PB65A PB65B PB67A PB67B VCCIO4 PB68A PB68B GNDIO4 PB69A PB69B PB70A PB70B PB71A PB71B VCCIO4 PB72A PB72B PB73A PB73B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 BDQ69 BDQ69 BDQ69 BDQ69 T C T C BDQS69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ69 BDQ69 T C BDQ69 BDQ69 BDQ69 BDQ69 T C T C BDQS51 BDQ51 BDQ51 BDQ51 T C T C BDQ51 BDQ51 T C BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C LFE2M35E/SE Dual Function VREF2_4/BDQ42 VREF1_4/BDQ42 Differential T C 4-136 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE Ball Number M12 M13 N14 N15 VCCIO N16 M16 L12 GNDIO L13 L16 K16 L14 VCCIO L15 K13 K14 K11 K15 GNDIO J16 H16 J15 J14 VCCIO J13 H13 H12 GNDIO VCCIO G16 VCCIO H15 E16 F15 GNDIO VCCIO F16 G15 J11 J12 G14 G13 GNDIO F14 F13 VCCIO GNDIO H11 Ball/Pad Function PR53B PR53A PR52B PR52A VCCIO8 PR51B PR51A PR50B GNDIO8 PR50A PR49B PR49A PR48B VCCIO8 PR48A PR47B PR47A RLM0_PLLCAP PR45B GNDIO3 PR45A PR44B PR44A PR43B VCCIO3 PR43A PR42B PR42A GNDIO3 VCCIO3 PR32B VCCIO3 PR32A PR31B PR31A GNDIO3 VCCIO3 PR28B PR28A PR27B PR27A PR25B PR25A GNDIO2 PR24B PR24A VCCIO2 GNDIO2 PR14B Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 C RDQ22 RDQ22 C (LVDS)* T (LVDS)* VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ22 PCLKT2_0/RDQ22 C T C (LVDS)* T (LVDS)* C T RLM1_SPLLT_FB_A RLM1_SPLLC_IN_A RLM1_SPLLT_IN_A T C (LVDS)* T (LVDS)* RLM1_SPLLC_FB_A C RLM0_GPLLT_IN_A RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A T C (LVDS)* T (LVDS)* RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A RLM0_GDLLT_IN_A RLM0_GPLLC_IN_A T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A C DI/CSSPI0N DOUT/CSON/CSSPI1N BUSY/SISPI T C T D4 D5 D6 D7 T C T C D1 D2 D3 C T C Dual Function WRITEN CS1N CSN D0/SPIFASTN Differential C T C T Ball/Pad Function PR68B PR68A PR67B PR67A VCCIO8 PR66B PR66A PR65B GNDIO8 PR65A PR64B PR64A PR63B VCCIO8 PR63A PR62B PR62A RLM0_PLLCAP PR60B GNDIO3 PR60A PR59B PR59A PR58B VCCIO3 PR58A PR57B PR57A GNDIO3 VCCIO3 PR42B VCCIO3 PR42A PR41B PR41A GNDIO3 VCCIO3 PR38B PR38A PR37B PR37A PR35B PR35A GNDIO2 PR34B PR34A VCCIO2 GNDIO2 PR14B Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 RDQ15 C RDQ32 RDQ32 C(LVDS)* T (LVDS)* VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ32 PCLKT2_0/RDQ32 C T C(LVDS)* T (LVDS)* C T RLM2_SPLLT_FB_A RLM2_SPLLC_IN_A RLM2_SPLLT_IN_A T C(LVDS)* T (LVDS)* RLM2_SPLLC_FB_A C RLM0_GPLLT_IN_A**/RDQ57 RLM0_GPLLC_FB_A/RDQ57 RLM0_GPLLT_FB_A/RDQS57*** T C(LVDS)* T (LVDS)* RLM0_GDLLT_FB_A/RDQ57 RLM0_GDLLC_IN_A**/RDQ57 RLM0_GDLLT_IN_A**/RDQ57 RLM0_GPLLC_IN_A**/RDQ57 T C(LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A/RDQ57 C DI/CSSPI0N DOUT/CSON/CSSPI1N BUSY/SISPI T C T D4 D5 D6 D7 T C T C D1 D2 D3 C T C LFE2M35E/SE Dual Function WRITEN CS1N CSN D0/SPIFASTN Differential C T C T 4-137 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE Ball Number G11 E13 F12 VCCIO F11 E12 D16 D15 C16 GNDIO B16 VCCIO F4 C15 A14 B15 B14 C12 A11 A12 B11 C11 B10 C10 A10 C14 B13 C13 A13 B9 D8 D9 C9 A5 C5 B5 C4 A8 C8 B8 C7 B7 A6 A7 C6 B4 B3 A4 C3 Ball/Pad Function PR14A PR13B PR13A VCCIO2 PR12B PR12A PR11B PR11A PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 Bank 2 2 2 2 2 2 2 2 2 2 2 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 T C T C C T C T C T T C T C C T C T VREF1_2 T RUM0_SPLLC_FB_A RUM0_SPLLT_FB_A RUM0_SPLLC_IN_A RUM0_SPLLT_IN_A VREF2_2 C T C (LVDS)* T (LVDS)* C Dual Function Differential T C (LVDS)* T (LVDS)* Ball/Pad Function PR14A PR13B PR13A VCCIO2 PR12B PR12A PR11B PR11A PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 Bank 2 2 2 2 2 2 2 2 2 2 2 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 T C T C C T C T C T T C T C C T C T VREF1_2 T RUM0_SPLLC_FB_A/RDQ15 RUM0_SPLLT_FB_A/RDQ15 RUM0_SPLLC_IN_A/RDQ15 RUM0_SPLLT_IN_A/RDQ15 VREF2_2 C T C(LVDS)* T (LVDS)* C LFE2M35E/SE Dual Function RDQ15 RDQ15 RDQ15 Differential T C(LVDS)* T (LVDS)* 4-138 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE Ball Number GNDIO VCCIO GNDIO VCCIO G10 G7 G9 H7 J10 K10 K8 E7 VCCIO E10 VCCIO E14 G12 VCCIO K12 M14 VCCIO M10 P12 VCCIO M7 P5 VCCIO K5 M3 VCCIO E3 G5 VCCIO T15 VCCIO G8 H10 J7 K9 A1 A15 A16 A3 A9 B12 B6 E15 E2 H14 Ball/Pad Function GNDIO1 VCCIO1 GNDIO0 VCCIO0 VCCPLL VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND Bank 1 0 0 0 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 Dual Function Differential Ball/Pad Function GNDIO1 VCCIO1 GNDIO0 VCCIO0 VCCPLL VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND Bank 1 0 0 0 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 LFE2M35E/SE Dual Function Differential 4-139 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA LFE2M20E/SE Ball Number H8 H9 J3 J8 J9 M15 M2 P9 R12 R5 T1 T16 D10 D11 D12 D13 D14 D4 D5 D6 D7 E11 E6 E8 E9 F10 F7 F8 F9 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank LFE2M35E/SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-140 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number D1 E1 F1 F2 F5 VCCIO G6 F4 F3 G1 GNDIO G2 H1 H2 VCCIO H7 H6 G3 H3 GNDIO H5 H4 J1 J2 J3 VCCIO J4 J7 J6 GNDIO VCCIO K1 K2 J5 K5 VCCIO K7 K6 L6 L7 GNDIO L1 L2 M7 VCCIO L5 L3 L4 M1 Ball/Pad Function PL2A PL2B PL3A PL3B PL4A VCCIO7 PL4B PL5A PL5B PL6A GNDIO7 PL6B PL7A PL7B VCCIO7 PL8A PL8B PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B PL13A VCCIO7 PL13B PL14A PL14B GNDIO7 VCCIO7 PL18A PL18B PL19A PL19B VCCIO7 PL20A PL20B PL21A PL21B GNDIO7 PL22A PL22B PL23A VCCIO7 PL23B PL24A PL24B PL25A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ22 LDQ22 LDQ22 PCLKT7_0/LDQ22 C T (LVDS)* C (LVDS)* T LDQS22 LDQ22 LDQ22 T (LVDS)* C (LVDS)* T LDQ22 LDQ22 LDQ22 LDQ22 T (LVDS)* C (LVDS)* T C LUM1_SPLLT_IN_A/LDQ22 LUM1_SPLLC_IN_A/LDQ22 LUM1_SPLLT_FB_A/LDQ22 LUM1_SPLLC_FB_A/LDQ22 T (LVDS)* C (LVDS)* T C C (LVDS)* T C LUM0_SPLLT_IN_A LUM0_SPLLC_IN_A LUM0_SPLLT_FB_A LUM0_SPLLC_FB_A T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ6 LDQ6 VREF2_7/LDQ6 VREF1_7/LDQ6 T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 LDQ6 C (LVDS)* T C LDQ6 LDQ6 LDQ6 LDQS6 C (LVDS)* T C T (LVDS)* Dual Function LDQ6 LDQ6 LDQ6 LDQ6 LDQ6 Differential T (LVDS)* C (LVDS)* T C T (LVDS)* Ball/Pad Function PL2A PL2B PL3A PL3B PL4A VCCIO7 PL4B PL5A PL5B PL6A GNDIO7 PL6B PL7A PL7B VCCIO7 PL8A PL8B PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B PL13A VCCIO7 PL13B PL14A PL14B GNDIO7 VCCIO7 PL28A PL28B PL29A PL29B VCCIO7 PL30A PL30B PL31A PL31B GNDIO7 PL32A PL32B PL33A VCCIO7 PL33B PL34A PL34B PL35A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ32 LDQ32 LDQ32 PCLKT7_0/LDQ32 C T (LVDS)* C (LVDS)* T LDQS32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T LDQ32 LDQ32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T C LUM1_SPLLT_IN_A/LDQ32 LUM1_SPLLC_IN_A/LDQ32 LUM1_SPLLT_FB_A/LDQ32 LUM1_SPLLC_FB_A/LDQ32 T (LVDS)* C (LVDS)* T C LDQ15 LDQ15 LDQ15 C (LVDS)* T C LUM0_SPLLT_IN_A/LDQ15 LUM0_SPLLC_IN_A/LDQ15 LUM0_SPLLT_FB_A/LDQ15 LUM0_SPLLC_FB_A/LDQ15 LDQ15 T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ6 LDQ6 VREF2_7/LDQ6 VREF1_7/LDQ6 T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 LDQ6 C (LVDS)* T C LDQ6 LDQ6 LDQ6 LDQS6 C (LVDS)* T C T (LVDS)* LFE2M35E/SE Dual Function LDQ6 LDQ6 LDQ6 LDQ6 LDQ6 Differential T (LVDS)* C (LVDS)* T C T (LVDS)* 4-141 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number GNDIO M2 M6 M5 M3 M4 VCCIO N7 GNDIO N6 N1 N2 VCCIO GNDIO P6 N5 P1 VCCIO P2 P3 P4 P5 GNDIO P7 R1 GNDIO R2 R3 R4 VCCIO R6 R5 T1 T2 GNDIO R7 T6 T7 U1 U2 VCCIO T3 U3 U6 U5 GNDIO V5 U4 V1 Ball/Pad Function GNDIO7 PL25B PL27A PL27B PL28A PL28B VCCIO6 PL31A GNDIO6 PL31B PL32A PL32B VCCIO6 GNDIO6 PL38A PL38B PL39A VCCIO6 PL39B PL40A PL40B PL41A GNDIO6 PL41B PL42A GNDIO6 PL42B PL43A PL43B VCCIO6 PL44A PL44B PL45A PL45B GNDIO6 LLM0_PLLCAP PL47A PL47B PL48A PL48B VCCIO6 PL49A PL49B PL50A PL50B GNDIO6 PL51A PL51B PL52A Bank 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQS51 LDQ51 LDQ51 T (LVDS)* C (LVDS)* T LDQ51 LDQ51 LDQ51 LDQ51 T (LVDS)* C (LVDS)* T C LDQ51 LDQ51 LDQ51 LDQ51 T (LVDS)* C (LVDS)* T C LLM0_GDLLT_IN_A** LLM0_GDLLC_IN_A** LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A** LLM0_GPLLT_FB_A LLM0_GPLLC_FB_A C (LVDS)* T C LDQ38 LLM0_GPLLT_IN_A** C T (LVDS)* LDQ38 LDQ38 LDQ38 LDQ38 C T (LVDS)* C (LVDS)* T LDQS38**** LDQ38 LDQ38 T (LVDS)* C (LVDS)* T LLM1_SPLLC_IN_A LLM1_SPLLT_FB_A LLM1_SPLLC_FB_A C (LVDS)* T C LLM1_SPLLT_IN_A T (LVDS)* PCLKC7_0/LDQ22 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T (LVDS)* C (LVDS)* T C Dual Function Differential Ball/Pad Function GNDIO7 PL35B PL37A PL37B PL38A PL38B VCCIO6 PL41A GNDIO6 PL41B PL42A PL42B VCCIO6 GNDIO6 PL48A PL48B PL49A VCCIO6 PL49B PL50A PL50B PL51A GNDIO6 PL51B PL57A GNDIO6 PL57B PL58A PL58B VCCIO6 PL59A PL59B PL60A PL60B GNDIO6 LLM0_PLLCAP PL62A PL62B PL63A PL63B VCCIO6 PL64A PL64B NC PL65B GNDIO6 PL66A PL66B PL67A Bank 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQS66 LDQ66 LDQ66 T (LVDS)* C (LVDS)* T LDQ66 C LDQ66 LDQ66 T (LVDS)* C (LVDS)* LDQ66 LDQ66 LDQ66 LDQ66 T (LVDS)* C (LVDS)* T C LLM0_GDLLT_IN_A**/LDQ57 LLM0_GDLLC_IN_A**/LDQ57 LLM0_GDLLT_FB_A/LDQ57 LLM0_GDLLC_FB_A/LDQ57 T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A**/LDQ57 LLM0_GPLLT_FB_A/LDQ57 LLM0_GPLLC_FB_A/LDQ57 C (LVDS)* T C LDQ48 LLM0_GPLLT_IN_A**/LDQS57**** C T (LVDS)* LDQ48 LDQ48 LDQ48 LDQ48 C T (LVDS)* C (LVDS)* T LDQS48**** LDQ48 LDQ48 T (LVDS)* C (LVDS)* T LLM2_SPLLC_IN_A LLM2_SPLLT_FB_A LLM2_SPLLC_FB_A C (LVDS)* T C LLM2_SPLLT_IN_A T (LVDS)* PCLKC7_0/LDQ32 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T (LVDS)* C (LVDS)* T C LFE2M35E/SE Dual Function Differential 4-142 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number VCCIO V3 W1 Y1 AA1 GNDIO AA2 V4 Y2 Y3 W3 W4 W5 Y4 W6 V6 AA3 VCCIO AB2 T8 U7 U8 GNDIO T9 V8 W8 Y6 VCCIO Y5 AB3 AB4 AB5 GNDIO AA6 V9 U9 VCCIO U10 T10 GNDIO W9 Y8 AA7 Y7 AB6 AB7 VCCIO GNDIO Ball/Pad Function VCCIO6 PL52B PL53A PL53B PL54A GNDIO6 PL54B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A VCCIO5 PB4B PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A VCCIO5 PB8B PB9A PB9B PB10A GNDIO5 PB10B PB13A PB13B VCCIO5 PB14A PB14B GNDIO5 PB15A PB15B PB16A PB16B PB17A PB17B VCCIO5 GNDIO5 Bank 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQS15**** BDQ15 VREF2_5/BDQ15 VREF1_5/BDQ15 PCLKT5_0/BDQ15 PCLKC5_0/BDQ15 T C T C T C BDQ15 BDQ15 T C BDQ6 BDQ15 BDQ15 C T C BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQS6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T LDQ51 C LDQ51 LDQ51 LDQ51 LDQ51 C T (LVDS)* C (LVDS)* T Dual Function Differential Ball/Pad Function VCCIO6 PL67B PL68A PL68B PL69A GNDIO6 PL69B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A VCCIO5 PB4B PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A VCCIO5 PB8B PB9A PB9B PB10A GNDIO5 PB10B PB31A PB31B VCCIO5 GNDIO5 PB32A PB32B GNDIO5 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO5 GNDIO5 Bank 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQS33**** BDQ33 VREF2_5/BDQ33 VREF1_5/BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 T C T C T C BDQ33 BDQ33 T C BDQ6 BDQ33 BDQ33 C T C BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQS6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T LDQ66 C LDQ66 LDQ66 LDQ66 LDQ66 C T (LVDS)* C (LVDS)* T LFE2M35E/SE Dual Function Differential 4-143 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number AA8 VCCIO AB8 AA9 Y9 AB9 GNDIO AB10 AA10 Y11 VCCIO GNDIO V10 U11 V11 W11 AA11 AB11 VCCIO T11 U12 GNDIO AA12 Y12 V12 W12 AB12 AA13 VCCIO T12 U13 V13 T13 GNDIO AB13 AB14 U14 T14 AA14 VCCIO Y14 W14 V14 AB15 GNDIO AA15 V15 U15 AB16 Ball/Pad Function PB22A VCCIO4 PB22B PB23A PB23B PB24A GNDIO4 PB24B PB25A PB25B VCCIO4 GNDIO4 PB29A PB29B PB30A PB30B PB31A PB31B VCCIO4 PB32A PB32B GNDIO4 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO4 PB36A PB36B PB37A PB37B GNDIO4 PB38A PB38B PB39A PB39B PB40A VCCIO4 PB40B PB41A PB41B PB42A GNDIO4 PB42B PB43A PB43B PB44A Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 BDQ42 BDQS42 C T C T BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 T C T C T BDQ33 BDQ33 BDQ33 BDQ33 T C T C BDQS33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C BDQ33 BDQ33 T C BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C BDQ24 BDQ24 BDQ24 C T C PCLKC4_0/BDQ24 VREF2_4/BDQ24 VREF1_4/BDQ24 BDQS24**** C T C T Dual Function PCLKT4_0/BDQ24 Differential T Ball/Pad Function PB40A VCCIO4 PB40B PB41A PB41B PB42A GNDIO4 PB42B PB43A PB43B VCCIO4 GNDIO4 PB47A PB47B PB48A PB48B PB49A PB49B VCCIO4 PB50A PB50B GNDIO4 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO4 PB54A PB54B PB55A PB55B GNDIO4 PB56A PB56B PB57A PB57B PB58A VCCIO4 PB58B PB59A PB59B PB60A GNDIO4 PB60B PB61A PB61B PB62A Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ60 BDQ60 BDQ60 BDQ60 C T C T BDQ60 BDQ60 BDQ60 BDQS60 C T C T BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T BDQ51 BDQ51 BDQ51 BDQ51 T C T C BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ51 BDQ51 T C BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ42 BDQ42 BDQ42 C T C PCLKC4_0/BDQ42 VREF2_4/BDQ42 VREF1_4/BDQ42 BDQS42**** C T C T LFE2M35E/SE Dual Function PCLKT4_0/BDQ42 Differential T 4-144 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number VCCIO AA16 AB17 AA17 Y15 GNDIO W15 AB20 AB21 AA21 AA20 AB19 AB18 VCCIO Y22 Y21 GNDIO Y17 Y18 Y16 W17 Y19 Y20 VCCIO W19 W18 V17 V18 GNDIO W20 V20 V19 V22 W22 U18 U22 GNDIO U20 U21 U17 U16 VCCIO T16 T17 T22 GNDIO R22 T15 R17 Ball/Pad Function VCCIO4 PB44B PB45A PB45B PB46A GNDIO4 PB46B PB47A PB47B PB48A PB48B PB49A PB49B VCCIO4 PB50A PB50B GNDIO4 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO4 PB54A PB54B PB55A PB55B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 PR53B PR53A PR52B PR52A VCCIO8 PR51B PR51A PR50B GNDIO8 PR50A PR49B PR49A Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 D4*** D5*** D6*** T C T D1*** D2*** D3*** C T C WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** C T C T BDQ51 BDQ51 BDQ51 BDQ51 T C T C BDQS51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ51 BDQ51 T C BDQ42 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 C T C T C T C BDQ42 BDQ42 BDQ42 BDQ42 C T C T Dual Function Differential Ball/Pad Function VCCIO4 PB62B PB63A PB63B PB64A GNDIO4 PB64B PB65A PB65B PB66A PB66B PB67A PB67B VCCIO4 PB68A PB68B GNDIO4 PB69A PB69B PB70A PB70B PB71A PB71B VCCIO4 PB72A PB72B PB73A PB73B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 PR68B PR68A PR67B PR67A VCCIO8 PR66B PR66A PR65B GNDIO8 PR65A PR64B PR64A Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 D4*** D5*** D6*** T C T D1*** D2*** D3*** C T C WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** C T C T BDQ69 BDQ69 BDQ69 BDQ69 T C T C BDQS69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ69 BDQ69 T C BDQ60 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 C T C T C T C BDQ60 BDQ60 BDQ60 BDQ60 C T C T LFE2M35E/SE Dual Function Differential 4-145 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number T20 VCCIO T21 R21 R20 R16 R18 GNDIO R19 P22 P21 P16 VCCIO P17 P20 P19 GNDIO P18 N16 GNDIO N22 N21 N17 N18 VCCIO M22 M21 M16 GNDIO M17 M20 M19 M18 VCCIO L16 L22 L21 K22 VCCIO K21 L17 L18 GNDIO L20 L19 K16 K17 VCCIO Ball/Pad Function PR48B VCCIO8 PR48A PR47B PR47A RLM0_PLLCAP PR45B GNDIO3 PR45A PR44B PR44A PR43B VCCIO3 PR43A PR42B PR42A GNDIO3 PR41B PR41A GNDIO3 PR40B PR40A PR39B PR39A VCCIO3 PR38B PR38A PR37B GNDIO3 PR37A PR36B PR36A PR35B VCCIO3 PR35A PR34B PR34A PR32B VCCIO3 PR32A PR31B PR31A GNDIO3 PR30B PR30A PR29B PR29A VCCIO3 Bank 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C (LVDS)* T (LVDS)* RLM1_SPLLT_FB_A RLM1_SPLLC_IN_A RLM1_SPLLT_IN_A T C (LVDS)* T (LVDS)* RDQ38 RDQ38 RDQ38 RLM1_SPLLC_FB_A T C (LVDS)* T (LVDS)* C RDQ38 RDQ38 RDQ38 RDQ38 T C (LVDS)* T (LVDS)* C RDQ38 RDQS38 RDQ38 C (LVDS)* T (LVDS)* C RDQ38 RDQ38 RDQ38 RDQ38 C (LVDS)* T (LVDS)* C T RDQ38 RDQ38 C T RLM0_GPLLT_IN_A** RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A T C (LVDS)* T (LVDS)* RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** RLM0_GPLLC_IN_A** T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A C DI/CSSPI0N*** DOUT/CSON/CSSPI1N*** BUSY/SISPI*** T C T Dual Function D7*** Differential C Ball/Pad Function PR63B VCCIO8 PR63A PR62B PR62A RLM0_PLLCAP PR60B GNDIO3 PR60A PR59B PR59A PR58B VCCIO3 PR58A PR57B PR57A GNDIO3 VCCIO3 PR51B PR51A GNDIO3 PR50B PR50A PR49B PR49A VCCIO3 PR48B PR48A PR47B GNDIO3 PR47A PR46B PR46A PR45B VCCIO3 PR45A PR44B PR44A PR42B VCCIO3 PR42A PR41B PR41A GNDIO3 PR40B PR40A PR39B PR39A VCCIO3 Bank 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 C T C (LVDS)* T (LVDS)* RLM2_SPLLT_FB_A RLM2_SPLLC_IN_A RLM2_SPLLT_IN_A T C (LVDS)* T (LVDS)* RDQ48 RDQ48 RDQ48 RLM2_SPLLC_FB_A T C (LVDS)* T (LVDS)* C RDQ48 RDQ48 RDQ48 RDQ48 T C (LVDS)* T (LVDS)* C RDQ48 RDQS48 RDQ48 C (LVDS)* T (LVDS)* C RDQ48 RDQ48 RDQ48 RDQ48 C (LVDS)* T (LVDS)* C T RDQ48 RDQ48 C T RLM0_GPLLT_IN_A**/RDQ57 RLM0_GPLLC_FB_A/RDQ57 RLM0_GPLLT_FB_A/RDQS57**** T C (LVDS)* T (LVDS)* RLM0_GDLLT_FB_A/RDQ57 RLM0_GDLLC_IN_A**/RDQ57 RLM0_GDLLT_IN_A**/RDQ57 RLM0_GPLLC_IN_A**/RDQ57 T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A/RDQ57 C DI/CSSPI0N*** DOUT/CSON/CSSPI1N*** BUSY/SISPI*** T C T LFE2M35E/SE Dual Function D7*** Differential C 4-146 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number J16 K18 J22 J21 H22 H21 GNDIO J17 J18 J20 J19 VCCIO H16 H17 G22 GNDIO G21 H20 H19 G16 VCCIO H18 F22 F21 GNDIO G20 VCCIO F20 G17 F17 GNDIO E22 D22 E20 D20 VCCIO D19 E19 F18 F19 E18 GNDIO D18 VCCIO F16 C22 A21 Ball/Pad Function PR28B PR28A PR27B PR27A PR25B PR25A GNDIO2 PR24B PR24A PR23B PR23A VCCIO2 PR22B PR22A PR21B GNDIO2 PR21A PR20B PR20A PR19B VCCIO2 PR19A PR18B PR18A GNDIO2 PR16B VCCIO2 PR16A PR15B PR15A GNDIO2 PR14B PR14A PR13B PR13A VCCIO2 PR12B PR12A PR11B PR11A PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 Bank 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 12 12 T VREF1_2 T RUM0_SPLLC_FB_A RUM0_SPLLT_FB_A RUM0_SPLLC_IN_A RUM0_SPLLT_IN_A VREF2_2 C T C (LVDS)* T (LVDS)* C C T C (LVDS)* T (LVDS)* C (LVDS)* T (LVDS)* T C RUM1_SPLLT_FB_A/RDQ22 RUM1_SPLLC_IN_A/RDQ22 RUM1_SPLLT_IN_A/RDQ22 T C (LVDS)* T (LVDS)* RDQ22 RDQ22 RDQ22 RUM1_SPLLC_FB_A/RDQ22 T C (LVDS)* T (LVDS)* C RDQ22 RDQS22 RDQ22 C (LVDS)* T (LVDS)* C RDQ22 RDQ22 RDQ22 RDQ22 C (LVDS)* T (LVDS)* C T Dual Function VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ22 PCLKT2_0/RDQ22 Differential C T C (LVDS)* T (LVDS)* C T Ball/Pad Function PR38B PR38A PR37B PR37A PR35B PR35A GNDIO2 PR34B PR34A PR33B PR33A VCCIO2 PR32B PR32A PR31B GNDIO2 PR31A PR30B PR30A PR29B VCCIO2 PR29A PR28B PR28A PR26B PR26A GNDIO2 PR25B PR25A VCCIO2 GNDIO2 PR14B PR14A PR13B PR13A VCCIO2 PR12B PR12A PR11B PR11A PR9B GNDIO2 PR9A XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 Bank 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 12 12 T VREF1_2 T RUM0_SPLLC_FB_A/RDQ15 RUM0_SPLLT_FB_A/RDQ15 RUM0_SPLLC_IN_A/RDQ15 RUM0_SPLLT_IN_A/RDQ15 VREF2_2 C T C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 RDQ15 C T C (LVDS)* T (LVDS)* RDQ23 RDQ23 C (LVDS)* T (LVDS)* RDQ23 T RDQ23 C RUM1_SPLLT_FB_A/RDQ32 RUM1_SPLLC_IN_A/RDQ32 RUM1_SPLLT_IN_A/RDQ32 T C (LVDS)* T (LVDS)* RDQ32 RDQ32 RDQ32 RUM1_SPLLC_FB_A/RDQ32 T C (LVDS)* T (LVDS)* C RDQ32 RDQS32 RDQ32 C (LVDS)* T (LVDS)* C RDQ32 RDQ32 RDQ32 RDQ32 C (LVDS)* T (LVDS)* C T LFE2M35E/SE Dual Function VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ32 PCLKT2_0/RDQ32 Differential C T C (LVDS)* T (LVDS)* C T 4-147 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number B22 B21 C19 A18 A19 B18 C18 B17 C17 A17 C21 B20 C20 A20 B16 E17 D17 C16 A12 C12 B12 C11 A15 C15 B15 C14 B14 A13 A14 C13 B11 B10 A11 C10 E13 D12 GNDIO A9 A8 A7 A6 VCCIO E12 Ball/Pad Function URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP 0 URC_SQ_VCCOB0 URC_SQ_HDOUTN 0 URC_SQ_VCCTX1 URC_SQ_HDOUTN 1 URC_SQ_VCCOB1 URC_SQ_HDOUTP 1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX 33 URC_SQ_REFCLK N URC_SQ_REFCLK P URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP 2 URC_SQ_VCCOB2 URC_SQ_HDOUTN 2 URC_SQ_VCCTX2 URC_SQ_HDOUTN 3 URC_SQ_VCCOB3 URC_SQ_HDOUTP 3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 PT28B PT28A GNDIO1 PT27B PT27A PT26B PT26A VCCIO1 PT25B Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 1 1 C C T C T C T T C T C C T C T C T T C T C C T C Dual Function Differential Ball/Pad Function URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP 0 URC_SQ_VCCOB0 URC_SQ_HDOUTN 0 URC_SQ_VCCTX1 URC_SQ_HDOUTN 1 URC_SQ_VCCOB1 URC_SQ_HDOUTP 1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX 33 URC_SQ_REFCLK N URC_SQ_REFCLK P URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP 2 URC_SQ_VCCOB2 URC_SQ_HDOUTN 2 URC_SQ_VCCTX2 URC_SQ_HDOUTN 3 URC_SQ_VCCOB3 URC_SQ_HDOUTP 3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 PT46B PT46A GNDIO1 PT45B PT45A PT44B PT44A VCCIO1 PT43B Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 1 1 C C T C T C T T C T C C T C T C T T C T C C T C LFE2M35E/SE Dual Function Differential 4-148 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number F12 A5 A4 GNDIO B7 B8 G11 E11 VCCIO D11 D10 F11 G10 G9 GNDIO F9 C9 D9 A2 VCCIO A3 B3 C4 E10 F10 C7 GNDIO B6 C6 VCCIO C5 C8 D8 E8 E9 F8 G8 GNDIO F7 G7 C3 D4 VCCIO F6 E6 E5 D6 Ball/Pad Function PT25A PT24B PT24A GNDIO1 PT23B PT23A PT22B PT22A VCCIO1 PT21B PT21A PT20A PT20B PT19B GNDIO0 PT19A PT18B PT18A PT17B VCCIO0 PT17A PT16B PT16A PT15B PT15A PT14B GNDIO0 PT14A PT13B VCCIO0 PT13A PT12B PT12A PT11B PT11A PT10B PT10A GNDIO0 PT9B PT9A PT8B PT8A VCCIO0 PT7B PT7A PT6B PT6A Bank 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T T C T C T T C T C T C T C PCLKT0_0 VREF2_0 VREF1_0 T C T C VREF2_1 VREF1_1 PCLKT1_0 PCLKC1_0 PCLKC0_0 C T T C C C T C T Dual Function Differential T C T Ball/Pad Function PT43A PT42B PT42A GNDIO1 PT41B PT41A PT40B PT40A VCCIO1 PT39B PT39A PT38A PT38B PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A PT32B GNDIO0 PT32A PT31B VCCIO0 PT31A PT30B PT30A PT29B PT29A GNDIO0 VCCIO0 PT10B PT10A GNDIO0 PT9B PT9A PT8B PT8A VCCIO0 PT7B PT7A PT6B PT6A Bank 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T T C T C T T C T C T C T C PCLKT0_0 VREF2_0 VREF1_0 T C T C VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T LFE2M35E/SE Dual Function Differential T C T 4-149 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number GNDIO D3 E3 D5 E4 VCCIO C2 B2 B1 C1 R8 H15 H8 R15 J10 J11 J12 J13 K14 K9 L14 L9 M14 M9 N14 N9 P10 P11 P12 P13 B5 B9 E7 H9 D13 E16 H14 E21 G18 J15 K19 N19 P15 T18 V21 AA18 R14 V16 W13 Ball/Pad Function GNDIO0 PT5B PT5A PT4B PT4A VCCIO0 PT3B PT3A PT2B PT2A VCCPLL VCCPLL VCCPLL VCCPLL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 C T C T C T C T Dual Function Differential Ball/Pad Function GNDIO0 PT5B PT5A PT4B PT4A VCCIO0 PT3B PT3A PT2B PT2A VCCPLL VCCPLL VCCPLL VCCPLL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 C T C T C T C T LFE2M35E/SE Dual Function Differential 4-150 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number AA5 R9 V7 W10 N4 P8 T5 V2 E2 G5 J8 K4 AA22 U19 H11 H12 L15 L8 M15 M8 R11 R12 A1 A10 A16 A22 AA19 AA4 AB1 AB22 B13 B19 B4 D16 D2 D21 D7 G19 G4 H10 H13 J14 J9 K10 K11 K12 K13 K15 K20 Ball/Pad Function VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 5 5 5 5 6 6 6 6 7 7 7 7 8 8 Dual Function Differential Ball/Pad Function VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 5 5 5 5 6 6 6 6 7 7 7 7 8 8 LFE2M35E/SE Dual Function Differential 4-151 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA LFE2M20E/SE Ball Number K3 K8 L10 L11 L12 L13 M10 M11 M12 M13 N10 N11 N12 N13 N15 N20 N3 N8 P14 P9 R10 R13 T19 T4 W16 W2 W21 W7 Y10 Y13 D15 G14 G15 D14 E15 E14 F15 F14 F13 G12 G13 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC Bank LFE2M35E/SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-152 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA LFE2M50E/SE Ball Number D1 E1 F1 F2 F5 VCCIO G6 F4 F3 G1 GNDIO G2 H1 H2 VCCIO H7 H6 G3 H3 GNDIO VCCIO H5 H4 J1 J2 GNDIO J3 J4 J7 VCCIO J6 GNDIO VCCIO K1 K2 J5 K5 VCCIO K7 K6 L6 L7 Ball/Pad Function PL2A PL2B PL3A PL3B PL4A VCCIO7 PL4B PL5A PL5B PL6A GNDIO7 PL6B PL7A PL7B VCCIO7 PL8A PL8B PL9A PL9B GNDIO7 VCCIO7 PL11A PL11B PL12A PL12B GNDIO7 PL13A PL13B PL14A VCCIO7 PL14B GNDIO7 VCCIO7 PL32A PL32B PL33A PL33B VCCIO7 PL34A PL34B PL35A PL35B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ36 LDQ36 LDQ36 LDQ36 T (LVDS)* C (LVDS)* T C LUM3_SPLLT_IN_A/LDQ36 LUM3_SPLLC_IN_A/LDQ36 LUM3_SPLLT_FB_A/LDQ36 LUM3_SPLLC_FB_A/LDQ36 T (LVDS)* C (LVDS)* T C C T (LVDS)* C (LVDS)* T LUM0_SPLLT_IN_A LUM0_SPLLC_IN_A LUM0_SPLLT_FB_A LUM0_SPLLC_FB_A T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 VREF2_7/LDQ6 VREF1_7/LDQ6 T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 LDQ6 C (LVDS)* T C LDQ6 LDQ6 LDQ6 LDQS6 C (LVDS)* T C T (LVDS)* Dual Function LDQ6 LDQ6 LDQ6 LDQ6 LDQ6 Differential T (LVDS)* C (LVDS)* T C T (LVDS)* 4-153 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number GNDIO L1 L2 M7 VCCIO L5 L3 L4 M1 GNDIO M2 M6 M5 M3 M4 VCCIO N7 GNDIO N6 N1 N2 VCCIO GNDIO P6 N5 P1 VCCIO P2 P3 P4 P5 GNDIO P7 VCCIO GNDIO R1 GNDIO R2 R3 R4 VCCIO R6 R5 Ball/Pad Function GNDIO7 PL36A PL36B PL37A VCCIO7 PL37B PL38A PL38B PL39A GNDIO7 PL39B PL41A PL41B PL42A PL42B VCCIO6 PL45A GNDIO6 PL45B PL46A PL46B VCCIO6 GNDIO6 PL52A PL52B PL53A VCCIO6 PL53B PL54A PL54B PL55A GNDIO6 PL55B VCCIO6 GNDIO6 PL62A GNDIO6 PL62B PL63A PL63B VCCIO6 PL64A PL64B Bank 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LLM0_GDLLT_IN_A** LLM0_GDLLC_IN_A** T (LVDS)* C (LVDS)* LLM0_GPLLC_IN_A** LLM0_GPLLT_FB_A LLM0_GPLLC_FB_A C (LVDS)* T C LLM0_GPLLT_IN_A** T (LVDS)* LDQ52 C LDQ52 LDQ52 LDQ52 LDQ52 C T (LVDS)* C (LVDS)* T LDQS52**** LDQ52 LDQ52 T (LVDS)* C (LVDS)* T LLM3_SPLLC_IN_A LLM3_SPLLT_FB_A LLM3_SPLLC_FB_A C (LVDS)* T C LLM3_SPLLT_IN_A T (LVDS)* PCLKC7_0/LDQ36 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T (LVDS)* C (LVDS)* T C LDQ36 LDQ36 LDQ36 PCLKT7_0/LDQ36 C T (LVDS)* C (LVDS)* T LDQS36 LDQ36 LDQ36 T (LVDS)* C (LVDS)* T Dual Function Differential 4-154 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number T1 T2 GNDIO R7 T6 T7 U1 U2 VCCIO T3 U3 U6 U5 GNDIO V5 U4 V1 VCCIO V3 W1 Y1 AA1 GNDIO AA2 V4 Y2 Y3 W3 W4 W5 Y4 W6 V6 AA3 AB2 VCCIO T8 U7 GNDIO U8 T9 V8 W8 Ball/Pad Function PL65A PL65B GNDIO6 LLM0_PLLCAP PL67A PL67B PL68A PL68B VCCIO6 PL69A PL69B PL70A PL70B GNDIO6 PL71A PL71B PL72A VCCIO6 PL72B PL73A PL73B PL74A GNDIO6 PL74B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B GNDIO5 PB6A PB6B PB7A PB7B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQS6 BDQ6 BDQ6 BDQ6 T C T C BDQ6 BDQ6 T C BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ71 C LDQ71 LDQ71 LDQ71 LDQ71 C T (LVDS)* C (LVDS)* T LDQS71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T LDQ71 LDQ71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T C LDQ71 LDQ71 LDQ71 LDQ71 T (LVDS)* C (LVDS)* T C Dual Function LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A Differential T C 4-155 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number Y6 Y5 VCCIO AB3 AB4 AB5 AA6 GNDIO VCCIO V9 U9 VCCIO U10 T10 GNDIO W9 Y8 AA7 Y7 AB6 AB7 VCCIO GNDIO AA8 VCCIO AB8 AA9 Y9 AB9 GNDIO AB10 AA10 Y11 VCCIO GNDIO V10 U11 V11 W11 AA11 AB11 VCCIO T11 Ball/Pad Function PB8A PB8B VCCIO5 PB9A PB9B PB10A PB10B GNDIO5 VCCIO5 PB40A PB40B VCCIO5 PB41A PB41B GNDIO5 PB42A PB42B PB43A PB43B PB44A PB44B VCCIO5 GNDIO5 PB49A VCCIO4 PB49B PB50A PB50B PB51A GNDIO4 PB51B PB52A PB52B VCCIO4 GNDIO4 PB56A PB56B PB57A PB57B PB58A PB58B VCCIO4 PB59A Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ60 T BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T C BDQ51 BDQ51 BDQ51 C T C PCLKC4_0/BDQ51 VREF2_4/BDQ51 VREF1_4/BDQ51 BDQS51**** C T C T PCLKT4_0/BDQ51 T BDQS42**** BDQ42 VREF2_5/BDQ42 VREF1_5/BDQ42 PCLKT5_0/BDQ42 PCLKC5_0/BDQ42 T C T C T C BDQ42 BDQ42 T C BDQ42 BDQ42 T C BDQ6 BDQ6 BDQ6 BDQ6 T C T C Dual Function BDQ6 BDQ6 Differential T C 4-156 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number U12 GNDIO AA12 Y12 V12 W12 AB12 AA13 VCCIO T12 U13 V13 T13 GNDIO AB13 AB14 U14 T14 AA14 VCCIO Y14 W14 V14 AB15 GNDIO AA15 V15 U15 AB16 VCCIO AA16 AB17 AA17 GNDIO W20 V20 V19 V22 W22 U18 U22 GNDIO U20 Ball/Pad Function PB59B GNDIO4 PB60A PB60B PB61A PB61B PB62A PB62B VCCIO4 PB63A PB63B PB64A PB64B GNDIO4 PB65A PB65B PB66A PB66B PB67A VCCIO4 PB67B PB68A PB68B PB69A GNDIO4 PB69B PB70A PB70B PB71A VCCIO4 PB71B PB72A PB72B GNDIO4 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 WRITEN*** Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 BDQ69 BDQ69 BDQ69 C T C BDQ69 BDQ69 BDQ69 BDQ69 C T C T BDQ69 BDQ69 BDQ69 BDQS69 C T C T BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T BDQ60 BDQ60 BDQ60 BDQ60 T C T C BDQS60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T C Dual Function BDQ60 Differential C 4-157 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number U21 U17 U16 VCCIO T16 T17 T22 GNDIO R22 T15 R17 T20 VCCIO T21 R21 R20 R16 R18 GNDIO R19 P22 P21 P16 VCCIO P17 P20 P19 GNDIO VCCIO P18 N16 GNDIO N22 N21 N17 N18 VCCIO M22 M21 M16 GNDIO M17 M20 Ball/Pad Function CS1N*** CSN*** D0/SPIFASTN*** VCCIO8 D1*** D2*** D3*** GNDIO8 D4*** D5*** D6*** D7*** VCCIO8 DI/CSSPI0N*** DOUT/CSON/CSSPI1N*** BUSY/SISPI*** RLM0_PLLCAP PR65B GNDIO3 PR65A PR64B PR64A PR63B VCCIO3 PR63A PR62B PR62A GNDIO3 VCCIO3 PR55B PR55A GNDIO3 PR54B PR54A PR53B PR53A VCCIO3 PR52B PR52A PR51B GNDIO3 PR51A PR50B Bank 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ52 RDQ52 T C (LVDS)* RDQ52 RDQS52 RDQ52 C (LVDS)* T (LVDS)* C RDQ52 RDQ52 RDQ52 RDQ52 C (LVDS)* T (LVDS)* C T RDQ52 RDQ52 C T RLM0_GPLLT_IN_A** RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A T C (LVDS)* T (LVDS)* RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** RLM0_GPLLC_IN_A** T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A C Dual Function Differential 4-158 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number M19 M18 VCCIO L16 L22 L21 GNDIO K22 VCCIO K21 L17 L18 GNDIO L20 L19 K16 K17 VCCIO J16 K18 J22 J21 H22 H21 GNDIO J17 J18 J20 J19 VCCIO H16 H17 G22 GNDIO G21 H20 H19 G16 VCCIO H18 F22 F21 G20 Ball/Pad Function PR50A PR49B VCCIO3 PR49A PR48B PR48A GNDIO3 PR46B VCCIO3 PR46A PR45B PR45A GNDIO3 PR44B PR44A PR43B PR43A VCCIO3 PR42B PR42A PR41B PR41A PR39B PR39A GNDIO2 PR38B PR38A PR37B PR37A VCCIO2 PR36B PR36A PR35B GNDIO2 PR35A PR34B PR34A PR33B VCCIO2 PR33A PR32B PR32A PR30B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RUM3_SPLLT_FB_A/RDQ36 RUM3_SPLLC_IN_A/RDQ36 RUM3_SPLLT_IN_A/RDQ36 RDQ27 T C (LVDS)* T (LVDS)* C RDQ36 RDQ36 RDQ36 RUM3_SPLLC_FB_A/RDQ36 T C (LVDS)* T (LVDS)* C RDQ36 RDQS36 RDQ36 C (LVDS)* T (LVDS)* C RDQ36 RDQ36 RDQ36 RDQ36 C (LVDS)* T (LVDS)* C T VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ36 PCLKT2_0/RDQ36 C T C (LVDS)* T (LVDS)* C T C T C (LVDS)* T (LVDS)* RLM3_SPLLT_FB_A RLM3_SPLLC_IN_A RLM3_SPLLT_IN_A T C (LVDS)* T (LVDS)* RLM3_SPLLC_FB_A C RDQ52 RDQ52 RDQ52 T C (LVDS)* T (LVDS)* Dual Function RDQ52 RDQ52 Differential T (LVDS)* C 4-159 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number F20 GNDIO G17 F17 VCCIO GNDIO E22 D22 VCCIO E20 D20 D19 GNDIO E19 F18 F19 VCCIO E18 GNDIO D18 VCCIO F16 C22 A21 B22 B21 C19 A18 A19 B18 C18 B17 C17 A17 C21 B20 C20 A20 B16 E17 D17 C16 A12 Ball/Pad Function PR30A GNDIO2 PR29B PR29A VCCIO2 GNDIO2 PR14B PR14A VCCIO2 PR13B PR13A PR12B GNDIO2 PR12A PR11B PR11A VCCIO2 PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 T C T T C T C C T C T VREF1_2 T VREF2_2 C RUM0_SPLLT_FB_A RUM0_SPLLC_IN_A RUM0_SPLLT_IN_A T C (LVDS)* T (LVDS)* RUM0_SPLLC_FB_A C (LVDS)* T (LVDS)* C C T RDQ27 RDQ27 C (LVDS)* T (LVDS)* Dual Function RDQ27 Differential T 4-160 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number C12 B12 C11 A15 C15 B15 C14 B14 A13 A14 C13 B11 B10 A11 C10 GNDIO VCCIO E13 D12 GNDIO A9 A8 A7 A6 VCCIO E12 F12 A5 A4 GNDIO B7 B8 G11 E11 VCCIO D11 D10 G10 F11 G9 GNDIO F9 C9 Ball/Pad Function URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 GNDIO1 VCCIO1 PT55B PT55A GNDIO1 PT54B PT54A PT53B PT53A VCCIO1 PT52B PT52A PT51B PT51A GNDIO1 PT50B PT50A PT49B PT49A VCCIO1 PT48B PT48A PT47B PT47A PT46B GNDIO0 PT46A PT45B Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 PCLKT0_0 VREF2_0 T C VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T C T C T C T C T C T T C T C C T C Dual Function Differential 4-161 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number D9 A2 VCCIO A3 B3 C4 E10 F10 C7 GNDIO B6 C6 VCCIO C5 C8 D8 E8 E9 GNDIO VCCIO F8 GNDIO G8 F7 G7 C3 VCCIO D4 F6 E6 E5 D6 D3 GNDIO E3 D5 VCCIO E4 C2 B2 B1 C1 J10 Ball/Pad Function PT45A PT44B VCCIO0 PT44A PT43B PT43A PT42B PT42A PT41B GNDIO0 PT41A PT40B VCCIO0 PT40A PT39B PT39A PT38B PT38A GNDIO0 VCCIO0 PT10B GNDIO0 PT10A PT9B PT9A PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A PT5B GNDIO0 PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T T C T C T C T C T C T C C T C T C T T C T C T C T C Dual Function VREF1_0 Differential T C 4-162 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number J11 J12 J13 K14 K9 L14 L9 M14 M9 N14 N9 P10 P11 P12 P13 B5 B9 E7 H9 D13 E16 H14 E21 G18 J15 K19 N19 P15 T18 V21 AA18 R14 V16 W13 AA5 R9 V7 W10 N4 P8 T5 V2 E2 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 Bank 0 0 0 0 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 Dual Function Differential 4-163 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number G5 J8 K4 AA22 U19 H11 H12 L15 L8 M15 M8 R11 R12 A1 A10 A16 A22 AA19 AA4 AB1 AB22 B13 B19 B4 D16 D2 D21 D7 G19 G4 H10 H13 J14 J9 K10 K11 K12 K13 K15 K20 K3 K8 L10 Ball/Pad Function VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 7 7 7 8 8 Dual Function Differential 4-164 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number L11 L12 L13 M10 M11 M12 M13 N10 N11 N12 N13 N15 N20 N3 N8 P14 P9 R10 R13 T19 T4 W16 W2 W21 W7 Y10 Y13 Y15 W15 AB20 AB21 AA21 AA20 AB19 AB18 Y22 Y21 Y17 Y18 Y16 W17 Y19 Y20 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential 4-165 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.) LFE2M50E/SE Ball Number W19 W18 V17 V18 D15 G14 G15 D14 E15 E14 F15 F14 F13 G12 G13 H8 H15 R8 R15 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCPLL VCCPLL VCCPLL VCCPLL Bank Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. ***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-166 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number C2 C1 F6 H9 D3 VCCIO D2 F5 H8 E3 GNDIO E2 J9 E4 VCCIO E1 D1 J8 F4 GNDIO F3 F1 G6 K9 G5 VCCIO G4 H5 H6 GNDIO J7 H4 H3 VCCIO G3 GNDIO G1 H1 J3 J4 VCCIO H2 J2 K7 J6 GNDIO Ball/Pad Function PL2A PL2B PL3A PL3B PL4A VCCIO7 PL4B PL5A PL5B PL6A GNDIO7 PL6B PL7A PL7B VCCIO7 PL8A PL8B PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B PL13A VCCIO7 PL13B PL14A PL14B GNDIO7 PL16A PL16B PL17A VCCIO7 PL17B GNDIO7 PL19A PL19B PL20A PL20B VCCIO7 PL21A PL21B PL22A PL22B GNDIO7 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ23 LDQ23 LDQ23 LDQ23 T (LVDS)* C (LVDS)* T C LDQ23 LDQ23 LDQ23 LDQ23 T (LVDS)* C (LVDS)* T C LDQ15 C (LVDS)* LDQ15 LDQ15 LDQ15 T C T (LVDS)* LDQ15 C LDQ15 LDQ15 C (LVDS)* T LDQ15 T (LVDS)* LUM0_SPLLT_IN_A/LDQ15 LUM0_SPLLC_IN_A/LDQ15 LUM0_SPLLT_FB_A/LDQ15 LUM0_SPLLC_FB_A/LDQ15 T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 VREF2_7/LDQ6 VREF1_7/LDQ6 T (LVDS)* C (LVDS)* T C LDQ6 LDQ6 LDQ6 C (LVDS)* T C LDQ6 LDQ6 LDQ6 LDQS6 C (LVDS)* T C T (LVDS)* Dual Function LDQ6 LDQ6 LDQ6 LDQ6 LDQ6 Differential T (LVDS)* C (LVDS)* T C T (LVDS)* Ball/Pad Function PL2A PL2B PL3A PL3B PL4A VCCIO7 PL4B PL5A PL5B PL6A GNDIO7 PL6B PL7A PL7B VCCIO7 PL8A PL8B PL9A PL9B GNDIO7 VCCIO7 PL11A PL11B PL12A PL12B GNDIO7 PL13A PL13B PL14A VCCIO7 PL14B GNDIO7 PL19A PL19B PL20A VCCIO7 PL20B GNDIO7 PL23A PL23B PL24A PL24B VCCIO7 PL25A PL25B PL26A PL26B GNDIO7 LFE2M50E/SE Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ27 LDQ27 LDQ27 LDQ27 T* C* T C LDQ27 LDQ27 LDQ27 LDQ27 T* C* T C C* T C T* C C* T T* LUM0_SPLLT_IN_A LUM0_SPLLC_IN_A LUM0_SPLLT_FB_A LUM0_SPLLC_FB_A T* C* T C LDQ6 LDQ6 VREF2_7/LDQ6 VREF1_7/LDQ6 T* C* T C LDQ6 LDQ6 LDQ6 C* T C LDQ6 LDQ6 LDQ6 LDQS6 C* T C T* Dual Function LDQ6 LDQ6 LDQ6 LDQ6 LDQ6 Differential T* C* T C T* 4-167 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number K5 L5 K4 VCCIO L4 K3 L3 J1 GNDIO K2 K1 L1 K8 M5 VCCIO M4 M3 L8 M6 GNDIO M1 N1 N3 VCCIO N2 N5 N4 M7 GNDIO M8 P3 P2 P5 N6 P4 VCCIO R3 P6 N7 P1 GNDIO R1 N8 R5 VCCIO T3 T4 P8 R6 Ball/Pad Function PL23A PL23B PL24A VCCIO7 PL24B PL25A PL25B PL26A GNDIO7 PL26B PL28A PL28B PL29A PL29B VCCIO7 PL30A PL30B PL31A PL31B GNDIO7 PL32A PL32B PL33A VCCIO7 PL33B PL34A PL34B PL35A GNDIO7 PL35B PL37A PL37B PL38A PL38B PL39A VCCIO6 PL39B PL40A NC PL41A GNDIO6 PL41B PL42A PL42B VCCIO6 PL44A PL44B PL45A PL45B Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ48 LDQ48 LDQ48 LDQ48 T (LVDS)* C (LVDS)* T C LLM2_SPLLC_IN_A LLM2_SPLLT_FB_A LLM2_SPLLC_FB_A C (LVDS)* T C LLM2_SPLLT_IN_A T (LVDS)* C (LVDS)* T PCLKC7_0/LDQ32 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ32 LDQ32 LDQ32 PCLKT7_0/LDQ32 C T (LVDS)* C (LVDS)* T LDQS32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T LDQ32 LDQ32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T C LDQ23 LUM1_SPLLT_IN_A/LDQ32 LUM1_SPLLC_IN_A/LDQ32 LUM1_SPLLT_FB_A/LDQ32 LUM1_SPLLC_FB_A/LDQ32 C T (LVDS)* C (LVDS)* T C LDQ23 LDQ23 LDQ23 LDQ23 C T (LVDS)* C (LVDS)* T Dual Function LDQS23 LDQ23 LDQ23 Differential T (LVDS)* C (LVDS)* T Ball/Pad Function PL27A PL27B PL28A VCCIO7 PL28B PL29A PL29B PL30A GNDIO7 PL30B PL32A PL32B PL33A PL33B VCCIO7 PL34A PL34B PL35A PL35B GNDIO7 PL36A PL36B PL37A VCCIO7 PL37B PL38A PL38B PL39A GNDIO7 PL39B PL41A PL41B PL42A PL42B PL43A VCCIO6 PL43B PL44A PL44B PL45A GNDIO6 PL45B PL46A PL46B VCCIO6 PL48A PL48B PL49A PL49B LFE2M50E/SE Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ52 LDQ52 LDQ52 LDQ52 T* C* T C LLM3_SPLLC_IN_A LLM3_SPLLT_FB_A LLM3_SPLLC_FB_A C* T C LLM3_SPLLT_IN_A C* T C T* PCLKC7_0/LDQ36 PCLKT6_0 PCLKC6_0 VREF2_6 VREF1_6 C T* C* T C T* LDQ36 LDQ36 LDQ36 PCLKT7_0/LDQ36 C T* C* T LDQS36 LDQ36 LDQ36 T* C* T LDQ36 LDQ36 LDQ36 LDQ36 T* C* T C LDQ27 LUM3_SPLLT_IN_A/LDQ36 LUM3_SPLLC_IN_A/LDQ36 LUM3_SPLLT_FB_A/LDQ36 LUM3_SPLLC_FB_A/LDQ36 C T* C* T C LDQ27 LDQ27 LDQ27 LDQ27 C T* C* T Dual Function LDQS27 LDQ27 LDQ27 Differential T* C* T 4-168 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number VCCIO T1 U1 R7 T5 GNDIO U3 U4 U5 VCCIO U6 U2 V1 W2 GNDIO V2 V4 VCCIO V3 W4 GNDIO W3 W1 Y1 VCCIO AA1 AB1 U7 V6 GNDIO T8 W5 Y4 U8 W6 VCCIO Y3 AA3 V7 Y5 GNDIO AB2 AA4 Y6 VCCIO U9 AA5 AA6 Ball/Pad Function VCCIO6 PL46A PL46B PL47A PL47B GNDIO6 PL48A PL48B PL49A VCCIO6 PL49B PL50A PL50B PL51A GNDIO6 PL51B PL55A VCCIO6 PL55B PL57A GNDIO6 PL57B PL58A PL58B VCCIO6 PL59A PL59B PL60A PL60B GNDIO6 LLM0_PLLCAP PL62A PL62B PL63A PL63B VCCIO6 PL64A PL64B NC PL65B GNDIO6 PL66A PL66B PL67A VCCIO6 PL67B PL68A PL68B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ66 LDQ66 LDQ66 C T (LVDS)* C (LVDS)* LDQS66 LDQ66 LDQ66 T (LVDS)* C (LVDS)* T LDQ66 C LDQ66 LDQ66 T (LVDS)* C (LVDS)* LDQ66 LDQ66 LDQ66 LDQ66 T (LVDS)* C (LVDS)* T C LLM0_GDLLT_IN_A**/LDQ57 LLM0_GDLLC_IN_A**/LDQ57 LLM0_GDLLT_FB_A/LDQ57 LLM0_GDLLC_FB_A/LDQ57 T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A**/LDQ57 LLM0_GPLLT_FB_A/LDQ57 LLM0_GPLLC_FB_A/LDQ57 C (LVDS)* T C LLM0_GPLLT_IN_A**/LDQS57**** T (LVDS)* LDQ57 C (LVDS)* LDQ48 LDQ57 C T (LVDS)* LDQ48 LDQ48 LDQ48 LDQ48 C T (LVDS)* C (LVDS)* T LDQS48 LDQ48 LDQ48 T (LVDS)* C (LVDS)* T LDQ48 LDQ48 LDQ48 LDQ48 T (LVDS)* C (LVDS)* T C Dual Function Differential Ball/Pad Function VCCIO6 PL50A PL50B PL51A PL51B GNDIO6 PL52A PL52B PL53A VCCIO6 PL53B PL54A PL54B PL55A GNDIO6 PL55B PL59A VCCIO6 PL59B GNDIO6 PL62A GNDIO6 PL62B PL63A PL63B VCCIO6 PL64A PL64B PL65A PL65B GNDIO6 LLM0_PLLCAP PL67A PL67B PL68A PL68B VCCIO6 PL69A PL69B PL70A PL70B GNDIO6 PL71A PL71B PL72A VCCIO6 PL72B PL73A PL73B LFE2M50E/SE Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ71 LDQ71 LDQ71 C T* C* LDQS71 LDQ71 LDQ71 T* C* T LDQ71 LDQ71 LDQ71 LDQ71 T* C* T C LDQ71 LDQ71 LDQ71 LDQ71 T* C* T C LLM0_GDLLT_IN_A LLM0_GDLLC_IN_A LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A T* C* T C LLM0_GPLLC_IN_A LLM0_GPLLT_FB_A LLM0_GPLLC_FB_A C* T C LLM0_GPLLT_IN_A T* C* LDQ52 C T* LDQ52 LDQ52 LDQ52 LDQ52 C T* C* T LDQS52 LDQ52 LDQ52 T* C* T LDQ52 LDQ52 LDQ52 LDQ52 T* C* T C Dual Function Differential 4-169 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number Y7 GNDIO V9 AC3 W8 AC4 V8 AA7 AB6 Y8 AD1 AD2 AC5 AA8 VCCIO AC6 W9 AB7 GNDIO Y9 AD3 AD4 AA9 W10 VCCIO AC7 Y10 AE2 AD5 GNDIO AE4 AE3 W11 AB8 AE5 AD6 VCCIO AA10 AC8 W12 GNDIO AC9 W13 AB10 AF3 AF4 VCCIO AF5 AF6 Ball/Pad Function PL69A GNDIO6 PL69B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A PB8B VCCIO5 PB9A PB9B PB10A PB10B GNDIO5 PB11A PB11B PB12A PB12B PB13A PB13B VCCIO5 PB14A PB14B PB15A GNDIO5 PB15B PB16A PB16B PB17A PB17B VCCIO5 PB18A PB18B Bank 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ15 BDQ15 T C BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 C T C T C BDQ15 BDQ15 BDQS15 T C T BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 T C T C T C BDQ6 BDQ6 BDQ6 BDQ6 T C T C BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 C T C T C BDQ6 BDQ6 BDQS6 T C T BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ66 C Dual Function LDQ66 Differential T Ball/Pad Function PL74A GNDIO6 PL74B TCK TDI TMS TDO VCCJ PB2A PB2B PB3A PB3B PB4A PB4B VCCIO5 PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A PB8B VCCIO5 PB9A PB9B PB10A PB10B GNDIO5 PB11A PB11B PB12A PB12B PB13A PB13B VCCIO5 PB14A PB14B PB15A GNDIO5 PB15B PB16A PB16B PB17A PB17B VCCIO5 PB18A PB18B LFE2M50E/SE Bank 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ15 BDQ15 T C BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 C T C T C BDQ15 BDQ15 BDQS15 T C T BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 BDQ15 T C T C T C BDQ6 BDQ6 BDQ6 BDQ6 T C T C BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 C T C T C BDQ6 BDQ6 BDQS6 T C T BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 BDQ6 T C T C T C LDQ71 C Dual Function LDQ71 Differential T 4-170 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number Y12 GNDIO AB11 AD7 AF7 AD8 AA12 AE8 VCCIO AF8 AD9 AC10 AC11 GNDIO AB12 AD10 Y13 AF9 VCCIO AE9 AF10 AE10 AD11 GNDIO AF11 VCCIO GNDIO AA13 AB13 W14 AC12 AF12 AD12 VCCIO GNDIO AC13 VCCIO Y14 AB20 AC14 AB14 GNDIO AA14 VCCIO GNDIO W17 AA19 Ball/Pad Function PB19A GNDIO5 PB19B PB20A PB20B PB21A PB21B PB22A VCCIO5 PB22B PB23A PB23B PB24A GNDIO5 PB24B PB25A PB25B PB26A VCCIO5 PB26B PB27A PB27B PB28A GNDIO5 PB28B VCCIO5 GNDIO5 PB33A PB33B PB34A PB34B PB35A PB35B VCCIO5 GNDIO5 PB40A VCCIO4 PB40B PB57A PB41B PB42A GNDIO4 PB42B VCCIO4 GNDIO4 PB65A PB65B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 BDQ69 BDQ69 T C BDQ42 C PCLKC4_0/BDQ42 BDQ60 VREF1_4/BDQ42 BDQS42**** C T C T PCLKT4_0/BDQ42 T BDQS33**** BDQ33 VREF2_5/BDQ33 VREF1_5/BDQ33 PCLKT5_0/BDQ33 PCLKC5_0/BDQ33 T C T C T C BDQ24 C BDQ24 BDQ24 BDQ24 BDQ24 C T C T BDQ24 BDQ24 BDQ24 BDQ24 C T C T BDQ24 BDQ24 BDQ24 BDQS24 C T C T BDQ24 BDQ24 BDQ24 BDQ24 BDQ24 T C T C T BDQ15 C Dual Function BDQ15 Differential T Ball/Pad Function PB19A GNDIO5 PB19B VCCIO5 GNDIO5 PB29A PB29B PB30A PB30B PB31A VCCIO5 PB31B PB32A PB32B PB33A GNDIO5 PB33B PB34A PB34B PB35A VCCIO5 PB35B PB36A PB36B PB37A GNDIO5 PB37B VCCIO5 GNDIO5 PB42A PB42B PB43A PB43B PB44A PB44B VCCIO5 GNDIO5 PB49A VCCIO4 PB49B PB50A PB50B PB51A GNDIO4 PB51B VCCIO4 GNDIO4 PB56A PB56B LFE2M50E/SE Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 BDQ60 BDQ60 T C BDQ51 C PCLKC4_0/BDQ51 VREF2_4/BDQ51 VREF1_4/BDQ51 BDQS51**** C T C T PCLKT4_0/BDQ51 T BDQS42**** BDQ42 VREF2_5/BDQ42 VREF1_5/BDQ42 PCLKT5_0/BDQ42 PCLKC5_0/BDQ42 T C T C T C BDQ33 C BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQS33 C T C T BDQ33 BDQ33 BDQ33 BDQ33 BDQ33 T C T C T BDQ15 C Dual Function BDQ15 Differential T 4-171 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number AC15 Y18 AB15 AC16 VCCIO AA17 AB16 GNDIO AA15 W16 Y15 AC17 AA18 Y17 GNDIO W15 AB17 GNDIO VCCIO V17 AA20 GNDIO AD13 AF14 AE13 AE14 AD16 AF17 AF16 AE17 AD17 AE18 AD18 AF18 AD14 AE15 AD15 AF15 AD19 AC19 AB19 AE19 AF23 AD23 AE23 AD24 AF20 AD20 Ball/Pad Function PB48A PB68B PB49A PB49B VCCIO4 PB60A PB50B GNDIO4 PB51A PB59B PB52A PB52B PB61A PB61B GNDIO4 PB54A PB54B GNDIO4 VCCIO4 PB73A PB73B GNDIO4 VCC PB47A NC PB41A VCC PB51B NC PB50A VCC PB53B NC PB53A VCC PB48B NC PB47B VCC PB57B PB59A VCCAUX PB64A NC PB66B VCC PB55A NC Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ51 T BDQ69 C BDQ60 T BDQ60 BDQ60 C T BDQ51 C BDQ51 C BDQ51 T BDQ51 C BDQ51 T BDQ51 C VREF2_4/BDQ42 T BDQ51 T BDQ69 BDQ69 T C BDQ51 BDQ51 T C BDQS51**** BDQ60 BDQ51 BDQ51 BDQ60 BDQ60 T C T C T C BDQS60**** BDQ51 T C Dual Function BDQ51 BDQ69 BDQ51 BDQ51 Differential T C T C Ball/Pad Function PB57A PB57B PB58A PB58B VCCIO4 PB59A PB59B GNDIO4 PB60A PB60B PB61A PB61B PB62A PB62B VCCIO4 PB63A PB63B GNDIO4 VCCIO4 PB72A PB72B GNDIO4 LRC_SQ_VCCRX3 LRC_SQ_HDINP3 LRC_SQ_VCCIB3 LRC_SQ_HDINN3 LRC_SQ_VCCTX3 LRC_SQ_HDOUTP3 LRC_SQ_VCCOB3 LRC_SQ_HDOUTN3 LRC_SQ_VCCTX2 LRC_SQ_HDOUTN2 LRC_SQ_VCCOB2 LRC_SQ_HDOUTP2 LRC_SQ_VCCRX2 LRC_SQ_HDINN2 LRC_SQ_VCCIB2 LRC_SQ_HDINP2 LRC_SQ_VCCP LRC_SQ_REFCLKP LRC_SQ_REFCLKN LRC_SQ_VCCAUX33 LRC_SQ_HDINP1 LRC_SQ_VCCIB1 LRC_SQ_HDINN1 LRC_SQ_VCCRX1 LRC_SQ_HDOUTP1 LRC_SQ_VCCOB1 LFE2M50E/SE Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 T C T T C T C T C C T C T BDQ69 BDQ69 T C BDQ60 BDQ60 T C BDQS60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 T C T C T C BDQ60 BDQ60 T C Dual Function BDQ60 BDQ60 BDQ60 BDQ60 Differential T C T C 4-172 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number AE20 AD21 AE21 AF22 AF21 AD22 AE24 AE25 AF24 AD25 AA21 AA22 AB23 AC26 AB24 AA23 AB25 GNDIO Y19 Y21 AB26 Y22 VCCIO W19 Y20 W22 GNDIO W18 Y23 AA24 W21 VCCIO V20 W23 Y24 V19 V21 GNDIO U19 AA26 Y26 V23 VCCIO U20 W24 V24 GNDIO U21 W25 Ball/Pad Function PB55B VCC PB63B NC PB62A VCC PB67B NC PB67A VCC CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 PR68B PR68A PR67B PR67A VCCIO8 PR66B PR66A PR65B GNDIO8 PR65A PR64B PR64A PR63B VCCIO8 PR63A PR62B PR62A RLM0_PLLCAP PR60B GNDIO3 PR60A PR59B PR59A PR58B VCCIO3 PR58A PR57B PR57A GNDIO3 PR56A PR55B Bank 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 RDQ57 RDQ57 T C (LVDS)* RLM0_GPLLT_IN_A**/RDQ57 RLM0_GPLLC_FB_A/RDQ57 RLM0_GPLLT_FB_A/RDQS57 T C (LVDS)* T (LVDS)* RLM0_GDLLT_FB_A/RDQ57 RLM0_GDLLC_IN_A**/RDQ57 RLM0_GDLLT_IN_A**/RDQ57 RLM0_GPLLC_IN_A**/RDQ57 T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A C DI/CSSPI0N*** DOUT/CSON/CSSPI1N*** BUSY/SISPI*** T C T D4*** D5*** D6*** D7*** T C T C D4*** D5*** D6*** D7*** VCCIO8 DI/CSSPI0N*** DOUT/CSON/ CSSPI1N*** BUSY/SISPI*** RLM0_PLLCAP PR65B GNDIO3 PR65A PR64B PR64A PR63B VCCIO3 PR63A PR62B PR62A GNDIO3 PR60A PR59B D1*** D2*** D3*** C T C D1*** D2*** D3*** WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** C T C T BDQ69 T BDQ69 C BDQ60 T BDQ60 C Dual Function BDQ51 Differential C Ball/Pad Function LRC_SQ_HDOUTN1 LRC_SQ_VCCTX1 LRC_SQ_HDOUTN0 LRC_SQ_VCCOB0 LRC_SQ_HDOUTP0 LRC_SQ_VCCTX0 LRC_SQ_HDINN0 LRC_SQ_VCCIB0 LRC_SQ_HDINP0 LRC_SQ_VCCRX0 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** LFE2M50E/SE Bank 13 13 13 13 13 13 13 13 13 13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 T C* RLM0_GPLLT_IN_A RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A T C* T* RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A RLM0_GDLLT_IN_A RLM0_GPLLC_IN_A T C* T* C RLM0_GDLLC_FB_A C T C T C Dual Function Differential C 4-173 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number W26 VCCIO U18 U22 V25 V26 U24 T24 GNDIO T22 T23 U25 U26 VCCIO T19 R19 R21 GNDIO R20 T26 R26 P21 VCCIO P19 R23 R24 R22 VCCIO N19 P23 P24 GNDIO N21 P22 N20 N22 VCCIO P25 P26 M21 N23 N24 N25 GNDIO M22 M24 M23 N26 Ball/Pad Function PR55A VCCIO3 PR54B PR54A PR53B PR53A PR51B PR51A GNDIO3 PR50B PR50A PR49B PR49A VCCIO3 PR48B PR48A PR47B GNDIO3 PR47A PR46B PR46A PR45B VCCIO3 PR45A PR44B PR44A PR42B VCCIO3 PR42A PR41B PR41A GNDIO3 PR40B PR40A PR39B PR39A VCCIO3 PR38B PR38A PR37B PR37A PR35B PR35A GNDIO2 PR34B PR34A PR33B PR33A Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 RDQ32 RDQ32 RDQ32 RDQ32 C (LVDS)* T (LVDS)* C T VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ32 PCLKT2_0/RDQ32 C T C (LVDS)* T (LVDS)* C T C T C (LVDS)* T (LVDS)* RLM2_SPLLT_FB_A RLM2_SPLLC_IN_A RLM2_SPLLT_IN_A T C (LVDS)* T (LVDS)* RLM2_SPLLC_FB_A C RDQ48 RDQ48 RDQ48 T C (LVDS)* T (LVDS)* RDQ48 RDQ48 RDQ48 RDQ48 T C (LVDS)* T (LVDS)* C RDQ48 RDQS48 RDQ48 C (LVDS)* T (LVDS)* C RDQ48 RDQ48 RDQ48 RDQ48 C (LVDS)* T (LVDS)* C T RDQ57 RDQ57 RDQ57 RDQ57 RDQ48 RDQ48 C T C (LVDS)* T (LVDS)* C T Dual Function RDQ57 Differential T (LVDS)* Ball/Pad Function PR59A VCCIO3 PR58B PR58A PR57B PR57A PR55B PR55A GNDIO3 PR54B PR54A PR53B PR53A VCCIO3 PR52B PR52A PR51B GNDIO3 PR51A PR50B PR50A PR49B VCCIO3 PR49A PR48B PR48A GNDIO3 PR46B VCCIO3 PR46A PR45B PR45A GNDIO3 PR44B PR44A PR43B PR43A VCCIO3 PR42B PR42A PR41B PR41A PR39B PR39A GNDIO2 PR38B PR38A PR37B PR37A LFE2M50E/SE Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 RDQ36 RDQ36 RDQ36 RDQ36 C* T* C T VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ36 PCLKT2_0/RDQ36 C T C* T* C T C T C* T* RLM3_SPLLT_FB_A RLM3_SPLLC_IN_A RLM3_SPLLT_IN_A T C* T* RLM3_SPLLC_FB_A C RDQ52 RDQ52 RDQ52 T C* T* RDQ52 RDQ52 RDQ52 RDQ52 T C* T* C RDQ52 RDQS52 RDQ52 C* T* C RDQ52 RDQ52 RDQ52 RDQ52 C* T* C T RDQ52 RDQ52 C T C* T* C T Dual Function Differential T* 4-174 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number VCCIO L22 L24 L23 GNDIO M20 M26 L26 K22 VCCIO M19 K25 K26 K24 K23 GNDIO L19 K21 J23 J24 VCCIO K20 J21 H21 GNDIO K18 H22 J20 J25 VCCIO J26 G21 J19 GNDIO H23 H24 H25 H26 VCCIO G22 K19 G24 G23 GNDIO J18 F22 F23 F24 Ball/Pad Function VCCIO2 PR32B PR32A PR31B GNDIO2 PR31A PR30B PR30A PR29B VCCIO2 PR29A PR28B PR28A PR26B PR26A GNDIO2 PR25B PR25A PR24B PR24A VCCIO2 PR23B PR23A PR22B GNDIO2 PR22A PR21B PR21A PR20B VCCIO2 PR20A PR19B PR19A GNDIO2 PR18B PR18A PR17B PR17A VCCIO2 PR16B PR16A PR15B PR15A GNDIO2 PR14B PR14A PR13B PR13A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ15 RDQ15 C (LVDS)* T (LVDS)* RDQ15 RDQ15 C T RDQ15 RDQ15 RDQ15 RDQS15 C T C (LVDS)* T (LVDS)* RDQ15 RDQ15 RDQ15 RDQ15 C T C (LVDS)* T (LVDS)* RDQ23 RDQ23 RDQ23 T C (LVDS)* T (LVDS)* RDQ23 RDQ23 RDQ23 RDQ23 T C (LVDS)* T (LVDS)* C RDQ23 RDQS23 RDQ23 C (LVDS)* T (LVDS)* C RDQ23 RDQ23 RDQ23 RDQ23 C (LVDS)* T (LVDS)* C T RUM1_SPLLT_FB_A/RDQ32 RUM1_SPLLC_IN_A/RDQ32 RUM1_SPLLT_IN_A/RDQ32 RDQ23 RDQ23 T C (LVDS)* T (LVDS)* C T RDQ32 RDQ32 RDQ32 RUM1_SPLLC_FB_A/RDQ32 T C (LVDS)* T (LVDS)* C RDQ32 RDQS32 RDQ32 C (LVDS)* T (LVDS)* C Dual Function Differential Ball/Pad Function VCCIO2 PR36B PR36A PR35B GNDIO2 PR35A PR34B PR34A PR33B VCCIO2 PR33A PR32B PR32A PR30B PR30A GNDIO2 PR29B PR29A PR28B PR28A VCCIO2 PR27B PR27A PR26B GNDIO2 PR26A PR25B PR25A PR24B VCCIO2 PR24A PR23B PR23A GNDIO2 PR21B PR21A PR20B PR20A VCCIO2 PR19B PR19A PR18B PR18A GNDIO2 PR14B PR14A VCCIO2 PR13B PR13A LFE2M50E/SE Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C* T* C T C T C* T* C T C* T* RDQ27 RDQ27 RDQ27 T C* T* RDQ27 RDQ27 RDQ27 RDQ27 T C* T* C RDQ27 RDQS27 RDQ27 C* T* C RDQ27 RDQ27 RDQ27 RDQ27 C* T* C T RUM3_SPLLT_FB_A/RDQ36 RUM3_SPLLC_IN_A/RDQ36 RUM3_SPLLT_IN_A/RDQ36 RDQ27 RDQ27 T C* T* C T RDQ36 RDQ36 RDQ36 RUM3_SPLLC_FB_A/RDQ36 T C* T* C RDQ36 RDQS36 RDQ36 C* T* C Dual Function Differential 4-175 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number VCCIO H20 F21 G26 F26 E24 GNDIO E23 VCCIO H19 C25 A24 B25 B24 C22 A21 A22 B21 C21 B20 C20 A20 C24 B23 C23 A23 B19 E19 D19 C19 A15 C15 B15 C14 A18 C18 B18 Ball/Pad Function VCCIO2 PR12B PR12A PR11B PR11A PR9B GNDIO2 PR9A VCCIO4 XRES URC_SQ_VCCRX 0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX 0 URC_SQ_HDOUT P0 URC_SQ_VCCOB 0 URC_SQ_HDOUT N0 URC_SQ_VCCTX 1 URC_SQ_HDOUT N1 URC_SQ_VCCOB 1 URC_SQ_HDOUT P1 URC_SQ_VCCRX 1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAU X33 URC_SQ_REFCL KN URC_SQ_REFCL KP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX 2 URC_SQ_HDOUT P2 URC_SQ_VCCOB 2 URC_SQ_HDOUT N2 Bank 2 2 2 2 2 2 2 4 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 C T C T C T T C T C C T C T VREF1_2 T VREF2_2 C RUM0_SPLLT_FB_A/RDQ15 RUM0_SPLLC_IN_A/RDQ15 RUM0_SPLLT_IN_A/RDQ15 T C (LVDS)* T (LVDS)* RUM0_SPLLC_FB_A/RDQ15 C Dual Function Differential Ball/Pad Function PR12B GNDIO2 PR12A PR11B PR11A VCCIO2 PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 LFE2M50E/SE Bank 2 2 2 2 2 2 2 2 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 C T C T C T T C T C C T C T VREF1_2 T VREF2_2 C RUM0_SPLLT_FB_A RUM0_SPLLC_IN_A RUM0_SPLLT_IN_A T C* T* RUM0_SPLLC_FB_A C Dual Function Differential 4-176 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number C17 B17 A16 A17 C16 B14 B13 A14 C13 E17 D17 GNDIO F17 D16 F19 F18 VCCIO E16 D15 G18 E15 GNDIO G17 E14 D14 D13 VCCIO F15 E12 H17 E13 C12 GNDIO G15 C11 F14 A12 VCCIO A11 D12 H16 H18 H15 A10 Ball/Pad Function URC_SQ_VCCTX 2 URC_SQ_HDOUT N3 URC_SQ_VCCOB 3 URC_SQ_HDOUT P3 URC_SQ_VCCTX 3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX 3 PT46B PT46A GNDIO1 PT45B PT45A PT44B PT44A VCCIO1 PT43B PT43A PT42B PT42A GNDIO1 PT41B PT41A PT40B PT40A VCCIO1 PT39B PT39A PT38B PT38A PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A PT32B Bank 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C PCLKT0_0 VREF2_0 VREF1_0 T C T C VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T C T C T C T C T C T T C T C Dual Function Differential Ball/Pad Function URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 GNDIO1 VCCIO1 PT55B PT55A GNDIO1 PT54B PT54A PT53B PT53A VCCIO1 PT52B PT52A PT51B PT51A GNDIO1 PT50B PT50A PT49B PT49A VCCIO1 PT48B PT48A PT47B PT47A PT46B GNDIO0 PT46A PT45B PT45A PT44B VCCIO0 PT44A PT43B PT43A PT42B PT42A PT41B LFE2M50E/SE Bank 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C PCLKT0_0 VREF2_0 VREF1_0 T C T C VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T C T C T C T C T C T T C T C Dual Function Differential 4-177 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number GNDIO B10 D11 VCCIO G14 E11 F13 D10 H14 GNDIO VCCIO A9 C10 GNDIO E8 B9 A8 VCCIO F12 E10 G13 C9 B8 GNDIO A7 D9 H13 D6 C7 VCCIO C8 G12 D8 H12 GNDIO A6 A5 A4 A3 VCCIO C6 F10 D7 H11 D5 GNDIO E6 G10 F9 Ball/Pad Function GNDIO0 PT32A PT31B VCCIO0 PT31A PT30B PT30A PT29B PT29A GNDIO0 VCCIO0 PT24B PT23B GNDIO0 PT23A PT22B PT22A VCCIO0 PT21B PT21A PT20B PT20A PT19B GNDIO0 PT19A PT18B PT18A PT17B PT17A VCCIO0 PT16B PT16A PT15B PT15A GNDIO0 PT14B PT14A PT13B PT13A VCCIO0 PT12B PT12A PT11B PT11A PT10B GNDIO0 PT10A PT9B PT9A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C C T C T C T C T T C T C T C T C T C T C T C C T C T C T T C Dual Function Differential Ball/Pad Function GNDIO0 PT41A PT40B VCCIO0 PT40A PT39B PT39A PT38B PT38A GNDIO0 VCCIO0 PT24B PT23B GNDIO0 PT23A PT22B PT22A VCCIO0 PT21B PT21A PT20B PT20A PT19B GNDIO0 PT19A PT18B PT18A PT17B PT17A VCCIO0 PT16B PT16A PT15B PT15A GNDIO0 PT14B PT14A PT13B PT13A VCCIO0 PT12B PT12A PT11B PT11A PT10B GNDIO0 PT10A PT9B PT9A LFE2M50E/SE Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C C T C T C T C T T C T C T C T C T C T C T C C T C T C T T C Dual Function Differential 4-178 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number H10 VCCIO E7 B3 C5 B2 C4 G9 GNDIO F7 C3 VCCIO D4 J10 F8 G8 G7 L12 L13 L14 L15 M11 M12 M15 M16 N11 N16 P11 P16 R11 R12 R15 R16 T12 T13 T14 T15 B12 B7 F11 J13 K12 D18 F16 J14 K15 G25 L21 M17 Ball/Pad Function PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A PT5B GNDIO0 PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 2 T C T C T T C T C T C T C Dual Function Differential C Ball/Pad Function PT8B VCCIO0 PT8A PT7B PT7A PT6B PT6A PT5B GNDIO0 PT5A PT4B VCCIO0 PT4A PT3B PT3A PT2B PT2A VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 LFE2M50E/SE Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 2 2 2 T C T C T T C T C T C T C Dual Function Differential C 4-179 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number M25 N18 P18 R17 R25 T21 Y25 AA16 AC18 U15 V14 AA11 V13 AE12 AE7 U12 P9 R10 R2 T6 Y2 G2 L6 M10 M2 N9 AC24 U17 J11 J12 J15 J16 L18 L9 M18 M9 R18 R9 T18 T9 V11 V12 V15 V16 A13 A19 A2 A25 AA2 Ball/Pad Function VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND Bank 2 2 3 3 3 3 3 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7 7 7 7 7 8 8 Dual Function Differential Ball/Pad Function VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND LFE2M50E/SE Bank 2 2 3 3 3 3 3 4 4 4 4 5 5 5 5 5 6 6 6 6 6 7 7 7 7 7 8 8 Dual Function Differential 4-180 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number AA25 AB18 AB22 AB5 AB9 AE1 AE11 AE16 AE22 AE26 AE6 AF13 AF19 AF2 AF25 B1 B11 B16 B22 B26 B6 E18 E22 E5 E9 F2 F25 G11 G16 J22 J5 K11 K13 K14 K16 L10 L11 L16 L17 L2 L20 L25 L7 M13 M14 N10 N12 N13 N14 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFE2M50E/SE Bank Dual Function Differential 4-181 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number N15 N17 P10 P12 P13 P14 P15 P17 R13 R14 T10 T11 T16 T17 T2 T20 T25 T7 U11 U13 U14 U16 V22 V5 Y11 Y16 AB3 AB4 AC1 AC2 B4 B5 C26 D20 D21 D22 D23 D24 D25 D26 E20 E21 E25 E26 F20 G20 K10 K17 R4 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC LFE2M50E/SE Bank Dual Function Differential 4-182 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE Ball Number U10 U23 V10 W7 AB21 AC20 AC21 AC22 AC23 AC25 AD26 W20 H7 K6 P7 R8 V18 P20 J17 G19 Ball/Pad Function NC NC NC NC PB69B PB58A PB63A PB69A PB71A PB71B PB70B PB72B L_VCCPLL L_VCCPLL L_VCCPLL L_VCCPLL R_VCCPLL R_VCCPLL R_VCCPLL R_VCCPLL Bank 4 4 4 4 4 4 4 4 BDQ69 BDQ60 BDQ60 BDQS69**** BDQ69 BDQ69 BDQ69 BDQ69 C T T T T C C C Dual Function Differential Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC L_VCCPLL L_VCCPLL L_VCCPLL L_VCCPLL R_VCCPLL R_VCCPLL R_VCCPLL R_VCCPLL LFE2M50E/SE Bank Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-183 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number VCCIO D2 D3 GNDIO J8 H7 E3 E4 GNDIO G6 F5 E2 D1 G5 G4 K7 K8 E1 F2 F1 G3 VCCIO H5 H4 J5 J4 GNDIO G2 G1 L9 L7 K6 K5 L8 L6 H3 H2 N8 M9 J3 VCCIO Ball/Pad Function VCCIO7 PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B GNDIO7 PL13A PL13B PL14A PL14B NC NC NC NC NC NC NC NC VCCIO7 PL15A PL15B PL16A PL16B GNDIO7 NC NC NC NC NC NC NC NC PL18A PL18B PL19A PL19B PL20A VCCIO7 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 C T (LVDS)* T (LVDS)* C (LVDS)* T T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C LUM0_SPLLT_IN_A LUM0_SPLLC_IN_A LUM0_SPLLT_FB_A LUM0_SPLLC_FB_A T (LVDS)* C (LVDS)* T C VREF2_7/LDQ6 VREF1_7/LDQ6 T C Dual Function Differential Ball/Pad Function VCCIO7 PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B VCCIO7 PL13A PL13B PL14A PL14B GNDIO7 PL15A PL15B PL16A VCCIO7 PL16B PL17A PL17B PL18A GNDIO7 PL18B VCCIO7 PL21A PL21B PL22A PL22B GNDIO7 PL24A PL24B PL25A PL25B VCCIO7 PL26A PL26B PL27A PL27B GNDIO7 PL28A PL28B PL29A VCCIO7 PL29B PL30A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ28 LDQ28 C T (LVDS)* LDQS28 LDQ28 LDQ28 T (LVDS)* C (LVDS)* T LDQ28 LDQ28 LDQ28 LDQ28 T (LVDS)* C (LVDS)* T C LDQ28 LDQ28 LDQ28 LDQ28 T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C LDQ15 C LDQ15 LDQ15 LDQ15 LDQ15 C T (LVDS)* C (LVDS)* T LDQS15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T LDQ15 LDQ15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T C LUM0_SPLLT_IN_A/LDQ15 LUM0_SPLLC_IN_A/LDQ15 LUM0_SPLLT_FB_A/LDQ15 LUM0_SPLLC_FB_A/LDQ15 T (LVDS)* C (LVDS)* T C VREF2_7 VREF1_7 T C LFE2M70E/SE Dual Function Differential 4-184 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number J2 H1 GNDIO J1 L5 L4 N9 N7 VCCIO K2 K1 P9 P7 GNDIO M6 M5 N5 VCCIO N6 M4 M3 P6 GNDIO P8 L3 L2 P5 P4 VCCIO L1 M2 R5 R4 GNDIO M1 N2 R8 VCCIO T9 P3 P2 N1 GNDIO P1 T5 T4 U7 Ball/Pad Function PL20B PL21A GNDIO7 PL21B PL23A PL23B PL24A PL24B VCCIO7 PL25A PL25B PL26A PL26B GNDIO7 PL27A PL27B PL28A VCCIO7 PL28B PL29A PL29B PL30A GNDIO7 PL30B PL32A PL32B PL33A PL33B VCCIO7 PL34A PL34B PL35A PL35B GNDIO7 PL36A PL36B PL37A VCCIO7 PL37B PL38A PL38B PL39A GNDIO7 PL39B PL41A PL41B PL42A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 PCLKC7_0/LDQ36 PCLKT6_0 PCLKC6_0 VREF2_6 C T (LVDS)* C (LVDS)* T LDQ36 LDQ36 LDQ36 PCLKT7_0/LDQ36 C T (LVDS)* C (LVDS)* T LDQS36 LDQ36 LDQ36 T (LVDS)* C (LVDS)* T LDQ36 LDQ36 LDQ36 LDQ36 T (LVDS)* C (LVDS)* T C LDQ27 LUM3_SPLLT_IN_A/LDQ36 LUM3_SPLLC_IN_A/LDQ36 LUM3_SPLLT_FB_A/LDQ36 LUM3_SPLLC_FB_A/LDQ36 C T (LVDS)* C (LVDS)* T C LDQ27 LDQ27 LDQ27 LDQ27 C T (LVDS)* C (LVDS)* T LDQS27 LDQ27 LDQ27 T (LVDS)* C (LVDS)* T LDQ27 LDQ27 LDQ27 LDQ27 T (LVDS)* C (LVDS)* T C LDQ27 LDQ27 LDQ27 LDQ27 T (LVDS)* C (LVDS)* T C C Dual Function Differential C (LVDS)* T Ball/Pad Function PL30B PL31A GNDIO7 PL31B PL33A PL33B PL34A PL34B VCCIO7 PL35A PL35B PL36A PL36B GNDIO7 PL37A PL37B PL38A VCCIO7 PL38B PL39A PL39B PL40A GNDIO7 PL40B PL42A PL42B PL43A PL43B VCCIO7 PL44A PL44B PL45A PL45B GNDIO7 PL46A PL46B PL47A VCCIO7 PL47B PL48A PL48B PL49A GNDIO7 PL49B PL51A PL51B PL52A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 PCLKC7_0/LDQ46 PCLKT6_0/LDQ55 PCLKC6_0/LDQ55 VREF2_6/LDQ55 C T (LVDS)* C (LVDS)* T LDQ46 LDQ46 LDQ46 PCLKT7_0/LDQ46 C T (LVDS)* C (LVDS)* T LDQS46 LDQ46 LDQ46 T (LVDS)* C (LVDS)* T LDQ46 LDQ46 LDQ46 LDQ46 T (LVDS)* C (LVDS)* T C LDQ37 LUM3_SPLLT_IN_A/LDQ46 LUM3_SPLLC_IN_A/LDQ46 LUM3_SPLLT_FB_A/LDQ46 LUM3_SPLLC_FB_A/LDQ46 C T (LVDS)* C (LVDS)* T C LDQ37 LDQ37 LDQ37 LDQ37 C T (LVDS)* C (LVDS)* T LDQS37 LDQ37 LDQ37 T (LVDS)* C (LVDS)* T LDQ37 LDQ37 LDQ37 LDQ37 T (LVDS)* C (LVDS)* T C LDQ37 LDQ37 LDQ37 LDQ37 T (LVDS)* C (LVDS)* T C LDQ28 C LFE2M70E/SE Dual Function LDQ28 LDQ28 Differential C (LVDS)* T 4-185 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number T8 R3 VCCIO R2 R1 T1 GNDIO T3 T2 U9 U8 VCCIO U5 U4 V9 V7 VCCIO U3 U2 V8 U6 GNDIO U1 V2 V5 VCCIO V6 V1 W1 W5 GNDIO W6 W3 W4 W2 Y4 Y1 VCCIO Y2 Y5 Y6 AA1 GNDIO AA2 Y3 AB1 Y9 Ball/Pad Function PL42B PL43A VCCIO6 PL43B PL44A PL44B GNDIO6 PL45A PL45B PL46A PL46B VCCIO6 PL48A PL48B PL49A PL49B VCCIO6 PL50A PL50B PL51A PL51B GNDIO6 PL52A PL52B PL53A VCCIO6 PL53B PL54A PL54B PL55A GNDIO6 PL55B PL57A PL57B PL58A PL58B PL59A VCCIO6 PL59B PL60A PL60B NC GNDIO6 NC NC NC NC Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 C (LVDS)* T C LDQ52 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ52 LDQ52 LDQ52 LDQ52 C T (LVDS)* C (LVDS)* T LDQS52 LDQ52 LDQ52 T (LVDS)* C (LVDS)* T LDQ52 LDQ52 LDQ52 LDQ52 T (LVDS)* C (LVDS)* T C LDQ52 LDQ52 LDQ52 LDQ52 T (LVDS)* C (LVDS)* T C LLM3_SPLLT_IN_A LLM3_SPLLC_IN_A LLM3_SPLLT_FB_A LLM3_SPLLC_FB_A T (LVDS)* C (LVDS)* T C C (LVDS)* T C Dual Function VREF1_6 Differential C T (LVDS)* Ball/Pad Function PL52B PL53A VCCIO6 PL53B PL54A PL54B GNDIO6 VCCIO6 PL57A PL57B PL58A PL58B GNDIO6 PL60A PL60B PL61A PL61B VCCIO6 PL62A PL62B PL63A PL63B GNDIO6 PL64A PL64B PL65A VCCIO6 PL65B PL66A PL66B PL67A GNDIO6 PL67B PL69A PL69B PL70A PL70B PL71A VCCIO6 PL71B PL72A PL72B PL73A GNDIO6 PL73B PL74A PL74B VCCIO6 PL75A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ73 T (LVDS)* LDQ73 LDQ73 LDQ73 C (LVDS)* T C LDQ73 LDQ73 LDQ73 LDQS73 C (LVDS)* T C T (LVDS)* LDQ64 LDQ73 LDQ73 LDQ73 LDQ73 LDQ73 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ64 LDQ64 LDQ64 LDQ64 C T (LVDS)* C (LVDS)* T LDQS64 LDQ64 LDQ64 T (LVDS)* C (LVDS)* T LDQ64 LDQ64 LDQ64 LDQ64 T (LVDS)* C (LVDS)* T C LDQ64 LDQ64 LDQ64 LDQ64 T (LVDS)* C (LVDS)* T C LLM3_SPLLT_IN_A/LDQ55 LLM3_SPLLC_IN_A/LDQ55 LLM3_SPLLT_FB_A/LDQ55 LLM3_SPLLC_FB_A/LDQ55 T (LVDS)* C (LVDS)* T C LDQ55 LDQ55 LDQ55 C (LVDS)* T C LFE2M70E/SE Dual Function VREF1_6/LDQ55 LDQ55 Differential C T (LVDS)* 4-186 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number Y8 Y7 AA7 AB2 AB3 AA5 AA6 AB4 AB5 AA8 AA9 AC1 GNDIO AC2 AC4 AC3 VCCIO AC7 AC6 AC5 AD3 GNDIO AB8 AD2 AD1 AE2 AE1 AF2 AF1 AG1 AH1 AK2 AJ1 AJ2 AH4 AK5 AK4 AJ5 AH5 AJ6 AH6 AK6 AH2 AJ3 AH3 AK3 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC PL62A GNDIO6 PL62B PL63A PL63B VCCIO6 PL64A PL64B PL65A PL65B GNDIO6 LLM0_PLLCAP PL67A PL67B TCK TDI TMS TDO VCCJ VCC PB11A NC PB11B VCC PB13A NC PB13B VCC PB14B NC PB14A VCC PB12B NC PB12A Bank 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 BDQ15 T BDQ15 C BDQ15 T BDQ15 C BDQ15 C BDQ15 T BDQ15 C BDQ15 T LDQ71 LDQ71 T (LVDS)* C (LVDS)* LLM0_GDLLT_IN_A** LLM0_GDLLC_IN_A** LLM0_GDLLT_FB_A LLM0_GDLLC_FB_A T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A** LLM0_GPLLT_FB_A LLM0_GPLLC_FB_A C (LVDS)* T C LLM0_GPLLT_IN_A** T (LVDS)* Dual Function Differential Ball/Pad Function PL75B PL76A PL76B GNDIO6 PL78A PL78B PL79A PL79B PL80A VCCIO6 PL80B PL81A PL81B PL82A GNDIO6 PL82B PL83A PL83B VCCIO6 PL84A PL84B PL85A PL85B GNDIO6 LLM0_PLLCAP PL87A PL87B TCK TDI TMS TDO VCCJ LLC_SQ_VCCRX3 LLC_SQ_HDINP3 LLC_SQ_VCCIB3 LLC_SQ_HDINN3 LLC_SQ_VCCTX3 LLC_SQ_HDOUTP3 LLC_SQ_VCCOB3 LLC_SQ_HDOUTN3 LLC_SQ_VCCTX2 LLC_SQ_HDOUTN2 LLC_SQ_VCCOB2 LLC_SQ_HDOUTP2 LLC_SQ_VCCRX2 LLC_SQ_HDINN2 LLC_SQ_VCCIB2 LLC_SQ_HDINP2 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 T C T C C T C T T C LLM0_GDLLT_IN_A**/LDQ82 LLM0_GDLLC_IN_A**/LDQ82 LLM0_GDLLT_FB_A/LDQ82 LLM0_GDLLC_FB_A/LDQ82 T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A**/LDQ82 LLM0_GPLLT_FB_A/LDQ82 LLM0_GPLLC_FB_A/LDQ82 C (LVDS)* T C LDQ82 LDQ82 LDQ82 LLM0_GPLLT_IN_A**/LDQS82 C (LVDS)* T C T (LVDS)* LDQ82 LDQ82 LDQ82 LDQ82 LDQ82 T (LVDS)* C (LVDS)* T C T (LVDS)* LFE2M70E/SE Dual Function LDQ73 LDQ73 LDQ73 Differential C (LVDS)* T C 4-187 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number AH7 AG7 AF7 AJ7 AK11 AH11 AJ11 AH12 AK8 AH8 AJ8 AH9 AJ9 AK10 AK9 AH10 AJ12 AJ13 AK12 AH13 AF10 AE8 AE11 VCCIO AD9 AE10 AD10 AE13 GNDIO AC12 AG2 AG3 AD13 VCCIO AC13 AE14 AC14 AF3 GNDIO AF4 VCCIO AG4 AG5 GNDIO VCCIO AD11 AF13 AF12 Ball/Pad Function VCC PB15A PB15B VCCAUX PB18A NC PB18B VCC PB16A NC PB16B VCC PB17B NC PB17A VCC PB19B NC PB19A VCC PB3A PB3B PB4A VCCIO5 PB4B PB5A PB5B PB6A GNDIO5 PB6B PB7A PB7B PB8A VCCIO5 PB8B PB9A PB9B PB10A GNDIO5 PB10B VCCIO5 PB20A PB20B GNDIO5 VCCIO5 PB24A PB24B PB25A Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQS24**** BDQ24 BDQ24 T C T BDQ24 BDQ24 T C BDQ6 C BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQ6 C T C T BDQ6 BDQ6 BDQ6 BDQS6 C T C T BDQ6 BDQ6 BDQ6 T C T BDQ15 T BDQ15 C BDQ15 T BDQ15 C BDQ15 C BDQ15 T BDQ15 C BDQ15 T BDQS15 BDQ15 T C Dual Function Differential Ball/Pad Function LLC_SQ_VCCP LLC_SQ_REFCLKP LLC_SQ_REFCLKN LLC_SQ_VCCAUX33 LLC_SQ_HDINP1 LLC_SQ_VCCIB1 LLC_SQ_HDINN1 LLC_SQ_VCCRX1 LLC_SQ_HDOUTP1 LLC_SQ_VCCOB1 LLC_SQ_HDOUTN1 LLC_SQ_VCCTX1 LLC_SQ_HDOUTN0 LLC_SQ_VCCOB0 LLC_SQ_HDOUTP0 LLC_SQ_VCCTX0 LLC_SQ_HDINN0 LLC_SQ_VCCIB0 LLC_SQ_HDINP0 LLC_SQ_VCCRX0 PB30A PB30B PB31A VCCIO5 PB31B PB32A PB32B PB33A GNDIO5 PB33B PB34A PB34B PB35A VCCIO5 PB35B PB36A PB36B PB37A GNDIO5 PB37B PB38A PB38B PB39A PB39B PB40A VCCIO5 Bank 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ42 BDQ42 BDQ42 T C T BDQ42 BDQ42 T C BDQ33 C BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQS33 C T C T BDQ33 BDQ33 BDQ33 T C T T C T C C T C T T C LFE2M70E/SE Dual Function Differential 4-188 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number AD14 AG8 AF8 AE15 VCCIO AC15 VCCIO GNDIO AD15 AF15 AG10 AG9 AH14 AG12 VCCIO AG15 AG13 GNDIO AF16 AH15 AC16 AE16 AG11 AF11 VCCIO GNDIO AJ14 VCCIO AK14 AK15 AK16 AF18 GNDIO AD16 AJ15 AG16 AE17 VCCIO AC17 AH16 AK17 AG20 GNDIO AG21 AG18 AJ16 AF21 AG22 Ball/Pad Function PB25B PB26A PB26B PB27A VCCIO5 PB27B VCCIO5 GNDIO5 PB38A PB38B PB39A PB39B PB40A PB40B VCCIO5 PB41A PB41B GNDIO5 PB42A PB42B PB43A PB43B PB44A PB44B VCCIO5 GNDIO5 PB49A VCCIO4 PB49B PB50A PB50B PB51A GNDIO4 PB51B PB52A PB52B PB53A VCCIO4 PB53B PB54A PB54B PB55A GNDIO4 PB55B PB56A PB56B PB57A PB57B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ51 BDQ60 BDQ60 BDQ60 BDQ60 C T C T C BDQ51 BDQ51 BDQ51 BDQ51 C T C T BDQ51 BDQ51 BDQ51 BDQ51 C T C T PCLKC4_0/BDQ51 VREF2_4/BDQ51 VREF1_4/BDQ51 BDQS51 C T C T PCLKT4_0/BDQ51 T BDQS42 BDQ42 VREF2_5/BDQ42 VREF1_5/BDQ42 PCLKT5_0/BDQ42 PCLKC5_0/BDQ42 T C T C T C BDQ42 BDQ42 T C BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 T C T C T C BDQ24 C Dual Function BDQ24 BDQ24 BDQ24 BDQ24 Differential C T C T Ball/Pad Function PB40B PB41A PB41B PB42A GNDIO5 PB42B VCCIO5 GNDIO5 PB47A PB47B PB48A PB48B PB49A PB49B VCCIO5 PB50A PB50B GNDIO5 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO5 GNDIO5 PB58A VCCIO4 PB58B PB59A PB59B PB60A GNDIO4 PB60B PB61A PB61B PB62A VCCIO4 PB62B PB63A PB63B PB64A GNDIO4 PB64B PB65A PB65B PB66A PB66B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ60 BDQ69 BDQ69 BDQ69 BDQ69 C T C T C BDQ60 BDQ60 BDQ60 BDQ60 C T C T BDQ60 BDQ60 BDQ60 BDQ60 C T C T PCLKC4_0/BDQ60 VREF2_4/BDQ60 VREF1_4/BDQ60 BDQS60 C T C T PCLKT4_0/BDQ60 T BDQS51 BDQ51 VREF2_5/BDQ51 VREF1_5/BDQ51 PCLKT5_0/BDQ51 PCLKC5_0/BDQ51 T C T C T C BDQ51 BDQ51 T C BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T C BDQ42 C LFE2M70E/SE Dual Function BDQ42 BDQ42 BDQ42 BDQS42**** Differential C T C T 4-189 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number AD17 AF19 VCCIO GNDIO AH17 AJ17 VCCIO AF26 AE25 GNDIO AD24 AE24 AD18 AC18 AE18 AG19 VCCIO GNDIO AC19 AD20 AB18 AC20 AE20 AE21 VCCIO AC23 AD23 GNDIO AH18 AK19 AJ18 AJ19 AH21 AK22 AK21 AJ22 AH22 AJ23 AH23 AK23 AH19 AJ20 AH20 AK20 AH24 AG24 AF24 AJ24 AK28 Ball/Pad Function PB58A PB58B VCCIO4 GNDIO4 PB62A PB62B VCCIO4 PB64A PB64B GNDIO4 PB65A PB65B PB66A PB66B PB67A PB67B VCCIO4 GNDIO4 PB69A PB69B PB70A PB70B PB71A PB71B VCCIO4 PB72A PB72B GNDIO4 LRC_SQ_VCCRX3 LRC_SQ_HDINP3 LRC_SQ_VCCIB3 LRC_SQ_HDINN3 LRC_SQ_VCCTX3 LRC_SQ_HDOUTP3 LRC_SQ_VCCOB3 LRC_SQ_HDOUTN3 LRC_SQ_VCCTX2 LRC_SQ_HDOUTN2 LRC_SQ_VCCOB2 LRC_SQ_HDOUTP2 LRC_SQ_VCCRX2 LRC_SQ_HDINN2 LRC_SQ_VCCIB2 LRC_SQ_HDINP2 LRC_SQ_VCCP LRC_SQ_REFCLKP LRC_SQ_REFCLKN LRC_SQ_VCCAUX33 LRC_SQ_HDINP1 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 T T C T C T C C T C T BDQ69 BDQ69 T C BDQS69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 T C T C T C BDQ60 BDQ60 T C BDQ60 BDQ60 T C Dual Function BDQ60 BDQ60 Differential T C Ball/Pad Function PB67A PB67B VCCIO4 GNDIO4 PB71A PB71B VCCIO4 PB73A PB73B GNDIO4 PB74A PB74B PB75A PB75B PB76A PB76B VCCIO4 GNDIO4 PB78A PB78B PB79A PB79B PB80A PB80B VCCIO4 PB81A PB81B GNDIO4 LRC_SQ_VCCRX3 LRC_SQ_HDINP3 LRC_SQ_VCCIB3 LRC_SQ_HDINN3 LRC_SQ_VCCTX3 LRC_SQ_HDOUTP3 LRC_SQ_VCCOB3 LRC_SQ_HDOUTN3 LRC_SQ_VCCTX2 LRC_SQ_HDOUTN2 LRC_SQ_VCCOB2 LRC_SQ_HDOUTP2 LRC_SQ_VCCRX2 LRC_SQ_HDINN2 LRC_SQ_VCCIB2 LRC_SQ_HDINP2 LRC_SQ_VCCP LRC_SQ_REFCLKP LRC_SQ_REFCLKN LRC_SQ_VCCAUX33 LRC_SQ_HDINP1 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 T T C T C T C C T C T BDQ78 BDQ78 T C BDQS78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T C BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T C BDQ69 BDQ69 T C BDQ69 BDQ69 T C LFE2M70E/SE Dual Function BDQ69 BDQ69 Differential T C 4-190 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number AH28 AJ28 AH29 AK25 AH25 AJ25 AH26 AJ26 AK27 AK26 AH27 AJ29 AJ30 AK29 AH30 AG27 AD25 AG28 AG30 AG29 AC24 AF27 GNDIO AF28 AE26 AB23 AF29 VCCIO AF30 AD26 AE29 GNDIO AE30 AD29 AC25 AD30 VCCIO AA22 AC26 AA23 AB22 AC27 GNDIO AC28 AC29 AC30 AB30 VCCIO AA30 Ball/Pad Function LRC_SQ_VCCIB1 LRC_SQ_HDINN1 LRC_SQ_VCCRX1 LRC_SQ_HDOUTP1 LRC_SQ_VCCOB1 LRC_SQ_HDOUTN1 LRC_SQ_VCCTX1 LRC_SQ_HDOUTN0 LRC_SQ_VCCOB0 LRC_SQ_HDOUTP0 LRC_SQ_VCCTX0 LRC_SQ_HDINN0 LRC_SQ_VCCIB0 LRC_SQ_HDINP0 LRC_SQ_VCCRX0 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** VCCIO8 D1*** D2*** D3*** GNDIO8 D4*** D5*** D6*** D7*** VCCIO8 DI/CSSPI0N*** DOUT/CSON/ CSSPI1N*** BUSY/SISPI*** RLM0_PLLCAP PR65B GNDIO3 PR65A PR64B PR64A PR63B VCCIO3 PR63A Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 RLM0_GPLLT_IN_A** T RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** RLM0_GPLLC_IN_A** T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A C T C T C C T C Dual Function Differential Ball/Pad Function LRC_SQ_VCCIB1 LRC_SQ_HDINN1 LRC_SQ_VCCRX1 LRC_SQ_HDOUTP1 LRC_SQ_VCCOB1 LRC_SQ_HDOUTN1 LRC_SQ_VCCTX1 LRC_SQ_HDOUTN0 LRC_SQ_VCCOB0 LRC_SQ_HDOUTP0 LRC_SQ_VCCTX0 LRC_SQ_HDINN0 LRC_SQ_VCCIB0 LRC_SQ_HDINP0 LRC_SQ_VCCRX0 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** VCCIO8 D1*** D2*** D3*** GNDIO8 D4*** D5*** D6*** D7*** VCCIO8 DI/CSSPI0N*** DOUT/CSON/ CSSPI1N*** BUSY/SISPI*** RLM0_PLLCAP PR85B GNDIO3 PR85A PR84B PR84A PR83B VCCIO3 PR83A Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 RLM0_GPLLT_IN_A**/RDQ82 T RLM0_GDLLT_FB_A/RDQ82 RLM0_GDLLC_IN_A**/RDQ82 RLM0_GDLLT_IN_A**/RDQ82 RLM0_GPLLC_IN_A**/RDQ82 T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A/RDQ82 C T C T C C T C LFE2M70E/SE Dual Function Differential 4-191 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number AB29 AB28 GNDIO Y22 Y23 AB26 AB27 Y24 Y25 AA29 Y28 Y30 Y29 W22 V22 Y27 Y26 W30 W29 W25 W26 U29 V29 VCCIO V30 U30 W27 W28 V24 V25 GNDIO U28 U27 U23 V23 VCCIO V26 U26 U25 GNDIO U24 T30 R30 T23 Ball/Pad Function PR62B PR62A GNDIO3 PR60B PR60A NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PR59B PR59A VCCIO3 PR58B PR58A PR57B PR57A PR55B PR55A GNDIO3 PR54B PR54A PR53B PR53A VCCIO3 PR52B PR52A PR51B GNDIO3 PR51A PR50B PR50A PR49B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ52 RDQ52 RDQ52 RDQ52 T C (LVDS)* T (LVDS)* C RDQ52 RDQS52 RDQ52 C (LVDS)* T (LVDS)* C RDQ52 RDQ52 RDQ52 RDQ52 C (LVDS)* T (LVDS)* C T RDQ52 RDQ52 C T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C T Dual Function RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A Differential C (LVDS)* T (LVDS)* Ball/Pad Function PR82B PR82A GNDIO3 PR81B PR81A PR80B PR80A VCCIO3 PR79B PR79A PR78B PR78A PR76B PR76A GNDIO3 PR75B PR75A PR74B VCCIO3 PR74A PR73B PR73A GNDIO3 PR72B PR72A PR71B PR71A VCCIO3 PR70B PR70A PR69B PR69A PR67B PR67A GNDIO3 PR66B PR66A PR65B PR65A VCCIO3 PR64B PR64A PR63B GNDIO3 PR63A PR62B PR62A PR61B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ64 RDQ64 RDQ64 RDQ64 T C (LVDS)* T (LVDS)* C RDQ64 RDQS64 RDQ64 C (LVDS)* T (LVDS)* C RDQ64 RDQ64 RDQ64 RDQ64 C (LVDS)* T (LVDS)* C T RDQ73 RDQ73 RDQ73 RDQ73 RDQ64 RDQ64 C T C (LVDS)* T (LVDS)* C T RDQ73 RDQ73 RDQ73 RDQ73 C T C (LVDS)* T (LVDS)* RDQ73 RDQ73 RDQS73 T C (LVDS)* T (LVDS)* RDQ73 RDQ73 RDQ73 C (LVDS)* T (LVDS)* C RDQ82 RDQ82 RDQ82 RDQ82 RDQ73 RDQ73 C T C (LVDS)* T (LVDS)* C T RDQ82 RDQ82 RDQ82 RDQ82 C T C (LVDS)* T (LVDS)* LFE2M70E/SE Dual Function RLM0_GPLLC_FB_A/RDQ82 RLM0_GPLLT_FB_A/RDQS82 Differential C (LVDS)* T (LVDS)* 4-192 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number VCCIO T22 T29 T28 R23 GNDIO VCCIO R22 P30 R29 T27 T26 GNDIO N30 N29 VCCIO R27 R28 P29 P28 M30 M29 GNDIO P23 P24 R26 P27 VCCIO P25 P26 K30 GNDIO K29 N22 P22 J30 VCCIO J29 N24 N23 N25 N26 GNDIO M27 M28 H30 G30 VCCIO Ball/Pad Function VCCIO3 PR49A PR48B PR48A PR46B GNDIO3 VCCIO3 PR46A PR45B PR45A PR44B PR44A GNDIO3 PR43B PR43A VCCIO3 PR42B PR42A PR41B PR41A PR39B PR39A GNDIO2 PR38B PR38A PR37B PR37A VCCIO2 PR36B PR36A PR35B GNDIO2 PR35A PR34B PR34A PR33B VCCIO2 PR33A PR32B PR32A PR30B PR30A GNDIO2 PR29B PR29A PR28B PR28A VCCIO2 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ27 RDQ27 RDQ27 RDQ27 C (LVDS)* T (LVDS)* C T RUM3_SPLLT_FB_A/RDQ36 RUM3_SPLLC_IN_A/RDQ36 RUM3_SPLLT_IN_A/RDQ36 RDQ27 RDQ27 T C (LVDS)* T (LVDS)* C T RDQ36 RDQ36 RDQ36 RUM3_SPLLC_FB_A/RDQ36 T C (LVDS)* T (LVDS)* C RDQ36 RDQS36 RDQ36 C (LVDS)* T (LVDS)* C RDQ36 RDQ36 RDQ36 RDQ36 C (LVDS)* T (LVDS)* C T VREF2_3 VREF1_3 PCLKC3_0 PCLKT3_0 PCLKC2_0/RDQ36 PCLKT2_0/RDQ36 C T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* T RLM3_SPLLT_FB_A RLM3_SPLLC_IN_A RLM3_SPLLT_IN_A T C (LVDS)* T (LVDS)* C RDQ52 RDQ52 RDQ52 RLM3_SPLLC_FB_A T C (LVDS)* T (LVDS)* C Dual Function Differential Ball/Pad Function VCCIO3 PR61A PR60B PR60A PR58B GNDIO3 PR58A PR57B PR57A PR56B VCCIO3 PR56A GNDIO3 PR53B PR53A VCCIO3 PR52B PR52A PR51B PR51A PR49B PR49A GNDIO2 PR48B PR48A PR47B PR47A VCCIO2 PR46B PR46A PR45B GNDIO2 PR45A PR44B PR44A PR43B VCCIO2 PR43A PR42B PR42A PR40B PR40A GNDIO2 PR39B PR39A PR38B PR38A VCCIO2 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ37 RDQ37 RDQ37 RDQ37 C (LVDS)* T (LVDS)* C T RUM3_SPLLT_FB_A/RDQ46 RUM3_SPLLC_IN_A/RDQ46 RUM3_SPLLT_IN_A/RDQ46 RDQ37 RDQ37 T C (LVDS)* T (LVDS)* C T RDQ46 RDQ46 RDQ46 RUM3_SPLLC_FB_A/RDQ46 T C (LVDS)* T (LVDS)* C RDQ46 RDQS46 RDQ46 C (LVDS)* T (LVDS)* C RDQ46 RDQ46 RDQ46 RDQ46 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ55 VREF1_3/RDQ55 PCLKC3_0/RDQ55 PCLKT3_0/RDQ55 PCLKC2_0/RDQ46 PCLKT2_0/RDQ46 C T C (LVDS)* T (LVDS)* C T RDQ55 RDQ55 C (LVDS)* T (LVDS)* RDQ55 T RLM3_SPLLT_FB_A/RDQ55 RLM3_SPLLC_IN_A/RDQ55 RLM3_SPLLT_IN_A/RDQ55 RDQ55 T C (LVDS)* T (LVDS)* C RDQ64 RDQ64 RDQ64 RLM3_SPLLC_FB_A/RDQ55 T C (LVDS)* T (LVDS)* C LFE2M70E/SE Dual Function Differential 4-193 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number M25 M26 L30 GNDIO L29 L28 L27 H29 VCCIO G29 L22 M22 F30 GNDIO F29 E30 E29 VCCIO L25 L26 H28 J28 G28 GNDIO G27 L24 L23 D30 D29 K24 K25 J27 K26 K23 K22 J22 VCCIO J23 J26 H26 H27 G26 Ball/Pad Function PR27B PR27A PR26B GNDIO2 PR26A PR25B PR25A PR24B VCCIO2 PR24A PR23B PR23A PR21B GNDIO2 PR21A PR20B PR20A VCCIO2 PR19B PR19A PR18B PR18A PR16B GNDIO2 PR16A NC NC NC NC NC NC NC NC PR15B PR15A PR14B VCCIO2 PR14A NC NC NC NC Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 T C (LVDS)* T (LVDS)* C T C (LVDS)* T (LVDS)* C C T C (LVDS)* T (LVDS)* T RDQ27 RDQ27 RDQ27 T C (LVDS)* T (LVDS)* C RDQ27 RDQ27 RDQ27 RDQ27 T C (LVDS)* T (LVDS)* C Dual Function RDQ27 RDQS27 RDQ27 Differential C (LVDS)* T (LVDS)* C Ball/Pad Function PR37B PR37A PR36B GNDIO2 PR36A PR35B PR35A PR34B VCCIO2 PR34A PR33B PR33A PR31B GNDIO2 PR31A PR30B PR30A PR29B PR29A VCCIO2 PR28B PR28A PR27B GNDIO2 PR27A PR26B PR26A PR25B VCCIO2 PR25A PR24B PR24A PR22B GNDIO2 PR22A PR21B PR21A PR20B VCCIO2 PR20A GNDIO2 PR17B PR17A PR16B PR16A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ15 RDQ15 RDQ15 RDQ15 C (LVDS)* T (LVDS)* C T T T C (LVDS)* T (LVDS)* C RDQ28 RDQ28 RDQ28 T C (LVDS)* T (LVDS)* C RDQ28 RDQ28 RDQ28 RDQ28 T C (LVDS)* T (LVDS)* C RDQ28 RDQS28 RDQ28 C (LVDS)* T (LVDS)* C RDQ28 RDQ28 C T RDQ28 RDQ28 C (LVDS)* T (LVDS)* RDQ28 T RDQ37 RDQ37 RDQ37 RDQ28 T C (LVDS)* T (LVDS)* C RDQ37 RDQ37 RDQ37 RDQ37 T C (LVDS)* T (LVDS)* C LFE2M70E/SE Dual Function RDQ37 RDQS37 RDQ37 Differential C (LVDS)* T (LVDS)* C 4-194 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number H23 H24 D28 E28 G24 H25 D27 GNDIO E27 F26 G25 F24 VCCIO GNDIO F25 VCCIO G23 C30 A29 B30 B29 C27 A26 A27 B26 C26 B25 C25 A25 C29 B28 C28 A28 B24 E24 D24 C24 A20 C20 B20 C19 A23 C23 B23 C22 B22 A21 Ball/Pad Function NC NC NC NC PR13B PR13A PR12B GNDIO2 PR12A PR11B PR11A PR9B VCCIO2 GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 Bank 2 2 2 2 2 2 2 2 2 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 C C T C T C T T C T C C T C T VREF1_2 T RUM0_SPLLT_FB_A RUM0_SPLLC_IN_A RUM0_SPLLT_IN_A VREF2_2 T C (LVDS)* T (LVDS)* C RUM0_SPLLC_FB_A C (LVDS)* T (LVDS)* C Dual Function Differential Ball/Pad Function VCCIO2 PR15B PR15A PR14B GNDIO2 PR14A PR13B PR13A PR12B VCCIO2 PR12A PR11B PR11A PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 C C T C T C T T C T C C T C T VREF1_2 T RUM0_SPLLT_FB_A/RDQ15 RUM0_SPLLC_IN_A/RDQ15 RUM0_SPLLT_IN_A/RDQ15 VREF2_2 T C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 RUM0_SPLLC_FB_A/RDQ15 T C (LVDS)* T (LVDS)* C RDQ15 RDQS15 RDQ15 C (LVDS)* T (LVDS)* C LFE2M70E/SE Dual Function Differential 4-195 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number A22 C21 B19 B18 A19 C18 D23 GNDIO E21 D26 E26 E23 G22 VCCIO D22 F21 G18 H18 D20 GNDIO D21 E20 E19 D19 VCCIO E18 D18 C17 A17 B17 GNDIO VCCIO J18 J19 H17 J17 F18 F17 A16 B16 G17 G16 VCCIO H16 F16 J16 G15 Ball/Pad Function URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 PT73B GNDIO1 PT73A PT72B PT72A PT71B PT71A VCCIO1 PT70B PT70A PT69B PT69A PT68B GNDIO1 PT68A PT67B PT67A PT66B VCCIO1 PT66A PT65B PT65A PT64B PT64A GNDIO1 VCCIO1 NC NC NC NC NC NC PT54B PT54A PT53B PT53A VCCIO1 PT52B PT52A PT51B PT51A Bank 12 12 12 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T T C T C T T C T C C T C T C T T C T C C T C Dual Function Differential T Ball/Pad Function URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 PT82B GNDIO1 PT82A PT81B PT81A PT80B VCCIO1 PT80A PT79B PT79A PT78B PT78A PT77B GNDIO1 PT77A PT76B PT76A PT75B VCCIO1 PT75A PT74B PT74A PT73B PT73A GNDIO1 VCCIO1 PT66B PT66A PT65B PT65A PT64B PT64A GNDIO1 PT63B PT63A PT62B PT62A VCCIO1 PT61B PT61A PT60B PT60A Bank 12 12 12 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C T C T C T T C T C T T C T C C T C T C T T C T C C T C LFE2M70E/SE Dual Function Differential T 4-196 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number GNDIO C16 D16 J15 H15 VCCIO A15 B15 F15 E16 C15 GNDIO D15 C14 E15 G14 VCCIO J14 F14 H14 A14 B14 D13 GNDIO F13 G13 VCCIO J11 D4 D5 E5 F6 GNDIO VCCIO F7 D8 GNDIO J13 G11 H13 H12 VCCIO E8 D9 D12 GNDIO E13 VCCIO GNDIO Ball/Pad Function GNDIO1 PT50B PT50A PT49B PT49A VCCIO1 PT48B PT48A PT47B PT47A PT46B GNDIO0 PT46A PT45B PT45A PT44B VCCIO0 PT44A PT43B PT43A PT42B PT42A PT41B GNDIO0 PT41A PT40B VCCIO0 PT40A PT38B PT38A PT37B PT37A GNDIO0 VCCIO0 PT34B PT34A GNDIO0 PT32B PT32A PT31B PT31A VCCIO0 PT30B PT30A PT28B GNDIO0 PT28A VCCIO0 GNDIO0 Bank 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C C T C T C T T C T C T T C T C T C T C PCLKT0_0 VREF2_0 VREF1_0 T C T C VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T Dual Function Differential Ball/Pad Function GNDIO1 PT59B PT59A PT58B PT58A VCCIO1 PT57B PT57A PT56B PT56A PT55B GNDIO0 PT55A PT54B PT54A PT53B VCCIO0 PT53A PT52B PT52A PT51B PT51A PT50B GNDIO0 PT50A PT49B VCCIO0 PT49A PT47B PT47A PT46B PT46A GNDIO0 VCCIO0 PT43B PT43A GNDIO0 PT41B PT41A PT40B PT40A VCCIO0 PT39B PT39A PT37B GNDIO0 PT37A VCCIO0 GNDIO0 Bank 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C C T C T C T T C T C T T C T C T C T C PCLKT0_0 VREF2_0 VREF1_0 T C T C VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T LFE2M70E/SE Dual Function Differential 4-197 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number J12 GNDIO VCCIO H10 E12 D11 H11 F11 C13 A12 B13 B12 C10 A9 A10 B9 C9 B8 C8 A8 C12 B11 C11 A11 B7 E7 D7 C7 A3 C3 B3 C2 A6 C6 B6 C5 B5 A4 A5 C4 B2 B1 A2 C1 L12 L13 L18 L19 M11 Ball/Pad Function PT5B GNDIO0 VCCIO0 PT5A PT4B PT4A PT3B PT3A VCC PT19A NC PT19B VCC PT17A NC PT17B VCC PT18B NC PT18A VCC PT16B NC PT16A VCCAUX PT15B PT15A VCC PT12A NC PT12B VCC PT14A NC PT14B VCC PT13B NC PT13A VCC PT11B NC PT11A VCC VCC VCC VCC VCC VCC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C C T C T C T T C T C C T C T T C T C T Dual Function Differential C Ball/Pad Function PT31B VCCIO0 PT31A PT30B PT30A PT29B PT29A ULC_SQ_VCCRX0 ULC_SQ_HDINP0 ULC_SQ_VCCIB0 ULC_SQ_HDINN0 ULC_SQ_VCCTX0 ULC_SQ_HDOUTP0 ULC_SQ_VCCOB0 ULC_SQ_HDOUTN0 ULC_SQ_VCCTX1 ULC_SQ_HDOUTN1 ULC_SQ_VCCOB1 ULC_SQ_HDOUTP1 ULC_SQ_VCCRX1 ULC_SQ_HDINN1 ULC_SQ_VCCIB1 ULC_SQ_HDINP1 ULC_SQ_VCCAUX33 ULC_SQ_REFCLKN ULC_SQ_REFCLKP ULC_SQ_VCCP ULC_SQ_HDINP2 ULC_SQ_VCCIB2 ULC_SQ_HDINN2 ULC_SQ_VCCRX2 ULC_SQ_HDOUTP2 ULC_SQ_VCCOB2 ULC_SQ_HDOUTN2 ULC_SQ_VCCTX2 ULC_SQ_HDOUTN3 ULC_SQ_VCCOB3 ULC_SQ_HDOUTP3 ULC_SQ_VCCTX3 ULC_SQ_HDINN3 ULC_SQ_VCCIB3 ULC_SQ_HDINP3 ULC_SQ_VCCRX3 VCC VCC VCC VCC VCC Bank 0 0 0 0 0 0 0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 T C T C C T C T C T T C T C C T C T T C T C T LFE2M70E/SE Dual Function Differential C 4-198 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number M12 M13 M14 M15 M16 M17 M18 M19 M20 N11 N12 N19 N20 P12 P19 R12 R19 T12 T19 U12 U19 V11 V12 V19 V20 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y12 Y13 Y18 Y19 D14 E6 E9 F12 K12 K13 D17 E22 E25 F19 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 Bank 0 0 0 0 0 0 1 1 1 1 Dual Function Differential Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 Bank 0 0 0 0 0 0 1 1 1 1 LFE2M70E/SE Dual Function Differential 4-199 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number K18 K19 F28 J25 K28 M21 M24 N21 N28 P21 R25 AA28 AB25 AE28 T25 U21 V21 V28 W21 W24 AA18 AA19 AE19 AF22 AG17 AG25 AA12 AA13 AE12 AF9 AG14 AG6 AA3 AB6 AE3 T6 U10 V10 V3 W10 W7 F3 J6 K3 M10 M7 N10 N3 P10 Ball/Pad Function VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 Bank 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 Dual Function Differential Ball/Pad Function VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 Bank 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 LFE2M70E/SE Dual Function Differential 4-200 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number R6 AA25 AD28 AA10 AA11 AA20 AA21 K10 K11 K20 K21 L10 L11 L20 L21 Y10 Y11 Y20 Y21 A1 A13 A18 A24 A30 A7 AA14 AA15 AA16 AA17 AA24 AA27 AA4 AB24 AB7 AD12 AD19 AD27 AE22 AE27 AE4 AE9 AF14 AF17 AF25 AF6 AJ10 AJ21 AJ27 AJ4 Ball/Pad Function VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 7 8 8 Dual Function Differential Ball/Pad Function VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank 7 8 8 LFE2M70E/SE Dual Function Differential 4-201 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number AK1 AK13 AK18 AK24 AK30 AK7 B10 B21 B27 B4 D25 D6 E14 E17 F22 F27 F4 F9 G12 G19 J24 J7 K14 K15 K16 K17 K27 K4 L14 L15 L16 L17 M23 M8 N14 N15 N16 N17 N27 N4 P11 P13 P14 P15 P16 P17 P18 P20 R10 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank LFE2M70E/SE Dual Function Differential 4-202 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number R11 R13 R14 R15 R16 R17 R18 R20 R21 R24 R7 T10 T11 T13 T14 T15 T16 T17 T18 T20 T21 T24 T7 U11 U13 U14 U15 U16 U17 U18 U20 V14 V15 V16 V17 V27 V4 W23 W8 Y14 Y15 Y16 Y17 AA26 AB10 AB11 AB12 AB13 AB14 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC PL73B NC NC NC NC Bank 6 LDQ71 C (LVDS)* Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC Bank LFE2M70E/SE Dual Function Differential 4-203 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number AB15 AB16 AB17 AB19 AB20 AB21 AB9 AC10 AC11 AC21 AC22 AC8 AC9 AD21 AD22 AD4 AD5 AD6 AD7 AD8 AE23 AE5 AE6 AE7 AF20 AF23 AF5 AG23 AG26 D10 E10 E11 F10 F20 F23 F8 G10 G20 G21 G7 G8 G9 H19 H20 H21 H22 H6 H8 H9 Ball/Pad Function NC NC NC NC NC NC PL73A PL74B NC NC NC PL70B PL74A NC NC PL68A PL68B PL71A PL72A PL72B NC PL69A PL70A PL71B NC NC PL69B NC NC PT10A PT9B PT10B PT9A NC NC PL6B NC NC NC PL8A PL6A PL5A NC NC NC NC PL8B PL5B PL2A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 0 0 0 0 7 7 7 7 7 7 7 LDQ6 LDQ6 LDQ6 C (LVDS)* C T (LVDS)* LDQ6 LDQS6**** LDQ6 T (LVDS)* T (LVDS)* T LDQ6 C (LVDS)* T C C T LDQ71 C (LVDS)* LDQ71 LDQ71 LDQ71 T (LVDS)* T C (LVDS)* LDQ71 LDQ71 LDQS71 LDQ71 LDQ71 T C T (LVDS)* T C LDQ71 LDQ71 C T LDQ71 LDQ71 T (LVDS)* C Dual Function Differential Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank LFE2M70E/SE Dual Function Differential 4-204 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA LFE2M50E/SE Ball Number J10 J20 J21 J9 K9 R9 U22 W9 N13 N18 V13 V18 Ball/Pad Function PL2B NC NC PL4A PL4B NC NC NC VCCPLL VCCPLL VCCPLL VCCPLL Bank 7 7 7 LDQ6 LDQ6 T (LVDS)* C (LVDS)* Dual Function LDQ6 Differential C (LVDS)* Ball/Pad Function NC NC NC NC NC NC NC NC VCCPLL VCCPLL VCCPLL VCCPLL Bank LFE2M70E/SE Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation. ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-205 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA LFE2M100E/SE Ball Number VCCIO D2 D3 GNDIO J8 H7 E3 E4 VCCIO G6 F5 E2 D1 GNDIO G5 G4 K7 VCCIO K8 E1 F2 F1 GNDIO G3 GNDIO VCCIO H5 H4 J5 J4 GNDIO G2 G1 L9 L7 VCCIO K6 K5 L8 L6 GNDIO Ball/Pad Function VCCIO7 PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B VCCIO7 PL13A PL13B PL14A PL14B GNDIO7 PL15A PL15B PL16A VCCIO7 PL16B PL17A PL17B PL18A GNDIO7 PL18B GNDIO7 VCCIO7 PL25A PL25B PL26A PL26B GNDIO7 PL28A PL28B PL29A PL29B VCCIO7 PL30A PL30B PL31A PL31B GNDIO7 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ32 LDQ32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T C LDQ32 LDQ32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T C LDQ23 LDQ23 LDQ23 LDQ23 T (LVDS)* C (LVDS)* T C LDQ15 C LDQ15 LDQ15 LDQ15 LDQ15 C T (LVDS)* C (LVDS)* T LDQS15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T LDQ15 LDQ15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T C LUM0_SPLLT_IN_A/LDQ15 LUM0_SPLLC_IN_A/LDQ15 LUM0_SPLLT_FB_A/LDQ15 LUM0_SPLLC_FB_A/LDQ15 T (LVDS)* C (LVDS)* T C VREF2_7 VREF1_7 T C Dual Function Differential 4-206 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number H3 H2 N8 VCCIO M9 J3 J2 H1 GNDIO J1 VCCIO GNDIO L5 L4 N9 N7 VCCIO K2 K1 P9 P7 GNDIO M6 M5 N5 VCCIO N6 M4 M3 P6 GNDIO P8 L3 L2 P5 P4 VCCIO L1 M2 R5 R4 GNDIO Ball/Pad Function PL32A PL32B PL33A VCCIO7 PL33B PL34A PL34B PL35A GNDIO7 PL35B VCCIO7 GNDIO7 PL41A PL41B PL42A PL42B VCCIO7 PL43A PL43B PL44A PL44B GNDIO7 PL45A PL45B PL46A VCCIO7 PL46B PL47A PL47B PL48A GNDIO7 PL48B PL50A PL50B PL51A PL51B VCCIO7 PL52A PL52B PL53A PL53B GNDIO7 Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ54 LDQ54 LDQ54 LDQ54 T (LVDS)* C (LVDS)* T C LDQ45 LUM3_SPLLT_IN_A/LDQ54 LUM3_SPLLC_IN_A/LDQ54 LUM3_SPLLT_FB_A/LDQ54 LUM3_SPLLC_FB_A/LDQ54 C T (LVDS)* C (LVDS)* T C LDQ45 LDQ45 LDQ45 LDQ45 C T (LVDS)* C (LVDS)* T LDQS45 LDQ45 LDQ45 T (LVDS)* C (LVDS)* T LDQ45 LDQ45 LDQ45 LDQ45 T (LVDS)* C (LVDS)* T C LDQ45 LDQ45 LDQ45 LDQ45 T (LVDS)* C (LVDS)* T C LDQ32 C LDQ32 LDQ32 C (LVDS)* T LDQ32 LDQ32 C T (LVDS)* Dual Function LDQS32 LDQ32 LDQ32 Differential T (LVDS)* C (LVDS)* T 4-207 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number M1 N2 R8 VCCIO T9 P3 P2 N1 GNDIO P1 T5 T4 U7 T8 R3 VCCIO R2 R1 T1 GNDIO VCCIO T3 T2 U9 U8 GNDIO U5 U4 V9 V7 VCCIO U3 U2 V8 U6 GNDIO U1 V2 V5 VCCIO V6 V1 W1 Ball/Pad Function PL54A PL54B PL55A VCCIO7 PL55B PL56A PL56B PL57A GNDIO7 PL57B PL59A PL59B PL60A PL60B PL61A VCCIO6 PL61B PL62A PL62B GNDIO6 VCCIO6 PL65A PL65B PL66A PL66B GNDIO6 PL68A PL68B PL69A PL69B VCCIO6 PL70A PL70B PL71A PL71B GNDIO6 PL72A PL72B PL73A VCCIO6 PL73B PL74A PL74B Bank 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ72 LDQ72 LDQ72 C T (LVDS)* C (LVDS)* LDQS72 LDQ72 LDQ72 T (LVDS)* C (LVDS)* T LDQ72 LDQ72 LDQ72 LDQ72 T (LVDS)* C (LVDS)* T C LDQ72 LDQ72 LDQ72 LDQ72 T (LVDS)* C (LVDS)* T C LLM4_SPLLT_IN_A/LDQ63 LLM4_SPLLC_IN_A/LDQ63 LLM4_SPLLT_FB_A/LDQ63 LLM4_SPLLC_FB_A/LDQ63 T (LVDS)* C (LVDS)* T C LDQ63 LDQ63 LDQ63 C (LVDS)* T C PCLKC7_0/LDQ54 PCLKT6_0/LDQ63 PCLKC6_0/LDQ63 VREF2_6/LDQ63 VREF1_6/LDQ63 LDQ63 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ54 LDQ54 LDQ54 PCLKT7_0/LDQ54 C T (LVDS)* C (LVDS)* T Dual Function LDQS54 LDQ54 LDQ54 Differential T (LVDS)* C (LVDS)* T 4-208 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number W5 GNDIO W6 W3 W4 W2 Y4 Y1 VCCIO Y2 Y5 Y6 AA1 GNDIO AA2 Y3 AB1 VCCIO Y9 Y8 Y7 AA7 GNDIO VCCIO AB2 AB3 AA5 AA6 AB4 VCCIO AB5 AA8 AA9 AC1 GNDIO AC2 AC4 AC3 VCCIO AC7 AC6 AC5 AD3 Ball/Pad Function PL75A GNDIO6 PL75B PL77A PL77B PL78A PL78B PL79A VCCIO6 PL79B PL80A PL80B PL81A GNDIO6 PL81B PL82A PL82B VCCIO6 PL83A PL83B PL84A PL84B GNDIO6 VCCIO6 PL95A PL95B PL96A PL96B PL97A VCCIO6 PL97B PL98A PL98B PL99A GNDIO6 PL99B PL100A PL100B VCCIO6 PL101A PL101B PL102A PL102B Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LLM0_GDLLT_IN_A**/LDQ99 LLM0_GDLLC_IN_A**/LDQ99 LLM0_GDLLT_FB_A/LDQ99 LLM0_GDLLC_FB_A/LDQ99 T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A**/LDQ99 LLM0_GPLLT_FB_A/LDQ99 LLM0_GPLLC_FB_A/LDQ99 C (LVDS)* T C LDQ99 LDQ99 LDQ99 LLM0_GPLLT_IN_A**/LDQS99 C (LVDS)* T C T (LVDS)* LDQ99 LDQ99 LDQ99 LDQ99 LDQ99 T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ81 LDQ81 LDQ81 LDQ81 T (LVDS)* C (LVDS)* T C LDQ81 LDQ81 LDQ81 C (LVDS)* T C LDQ81 LDQ81 LDQ81 LDQS81 C (LVDS)* T C T (LVDS)* LDQ72 LDQ81 LDQ81 LDQ81 LDQ81 LDQ81 C T (LVDS)* C (LVDS)* T C T (LVDS)* Dual Function LDQ72 Differential T 4-209 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number GNDIO AB8 AD2 AD1 AE2 AE1 AF2 AF1 AG1 AH1 AK2 AJ1 AJ2 AH4 AK5 AK4 AJ5 AH5 AJ6 AH6 AK6 AH2 AJ3 AH3 AK3 AH7 AG7 AF7 AJ7 AK11 AH11 AJ11 AH12 AK8 AH8 AJ8 AH9 AJ9 AK10 AK9 AH10 AJ12 AJ13 Ball/Pad Function GNDIO6 LLM0_PLLCAP PL104A PL104B TCK TDI TMS TDO VCCJ LLC_SQ_VCCRX3 LLC_SQ_HDINP3 LLC_SQ_VCCIB3 LLC_SQ_HDINN3 LLC_SQ_VCCTX3 LLC_SQ_HDOUTP3 LLC_SQ_VCCOB3 LLC_SQ_HDOUTN3 LLC_SQ_VCCTX2 LLC_SQ_HDOUTN2 LLC_SQ_VCCOB2 LLC_SQ_HDOUTP2 LLC_SQ_VCCRX2 LLC_SQ_HDINN2 LLC_SQ_VCCIB2 LLC_SQ_HDINP2 LLC_SQ_VCCP LLC_SQ_REFCLKP LLC_SQ_REFCLKN LLC_SQ_VCCAUX33 LLC_SQ_HDINP1 LLC_SQ_VCCIB1 LLC_SQ_HDINN1 LLC_SQ_VCCRX1 LLC_SQ_HDOUTP1 LLC_SQ_VCCOB1 LLC_SQ_HDOUTN1 LLC_SQ_VCCTX1 LLC_SQ_HDOUTN0 LLC_SQ_VCCOB0 LLC_SQ_HDOUTP0 LLC_SQ_VCCTX0 LLC_SQ_HDINN0 LLC_SQ_VCCIB0 Bank 6 6 6 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 C T C C T C T T C T C T C C T C T T C Dual Function Differential 4-210 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number AK12 AH13 AF10 AE8 AE11 VCCIO AD9 AE10 AD10 AE13 GNDIO AC12 AG2 AG3 AD13 VCCIO AC13 AE14 AC14 AF3 GNDIO AF4 AG4 AG5 GNDIO AD11 AF13 AF12 VCCIO AD14 AG8 AF8 AE15 GNDIO AC15 VCCIO GNDIO AD15 AF15 AG10 Ball/Pad Function LLC_SQ_HDINP0 LLC_SQ_VCCRX0 PB30A PB30B PB31A VCCIO5 PB31B PB32A PB32B PB33A GNDIO5 PB33B PB34A PB34B PB35A VCCIO5 PB35B PB36A PB36B PB37A GNDIO5 PB37B PB38A PB38B GNDIO5 PB48A PB48B PB49A VCCIO5 PB49B PB50A PB50B PB51A GNDIO5 PB51B VCCIO5 GNDIO5 PB56A PB56B PB57A Bank 14 14 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ60 BDQ60 BDQ60 T C T BDQ51 C BDQ51 BDQ51 BDQ51 BDQS51**** C T C T BDQ51 BDQ51 BDQ51 T C T BDQ42 BDQ42 T C BDQ33 C BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQ33 C T C T BDQ33 BDQ33 BDQ33 BDQS33 C T C T BDQ33 BDQ33 BDQ33 T C T Dual Function Differential T 4-211 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number AG9 AH14 AG12 VCCIO AG15 AG13 GNDIO AF16 AH15 AC16 AE16 AG11 AF11 VCCIO GNDIO AJ14 VCCIO AK14 AK15 AK16 AF18 GNDIO AD16 AJ15 AG16 AE17 VCCIO AC17 AH16 AK17 AG20 GNDIO AG21 AG18 AJ16 AF21 AG22 AD17 AF19 VCCIO GNDIO AH17 AJ17 Ball/Pad Function PB57B PB58A PB58B VCCIO5 PB59A PB59B GNDIO5 PB60A PB60B PB61A PB61B PB62A PB62B VCCIO5 GNDIO5 PB67A VCCIO4 PB67B PB68A PB68B PB69A GNDIO4 PB69B PB70A PB70B PB71A VCCIO4 PB71B PB72A PB72B PB73A GNDIO4 PB73B PB74A PB74B PB75A PB75B PB76A PB76B VCCIO4 GNDIO4 PB80A PB80B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ78 BDQ78 T C BDQ69 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 C T C T C T C BDQ69 BDQ69 BDQ69 BDQ69 C T C T BDQ69 BDQ69 BDQ69 BDQ69 C T C T PCLKC4_0/BDQ69 VREF2_4/BDQ69 VREF1_4/BDQ69 BDQS69 C T C T PCLKT4_0/BDQ69 T BDQS60 BDQ60 VREF2_5/BDQ60 VREF1_5/BDQ60 PCLKT5_0/BDQ60 PCLKC5_0/BDQ60 T C T C T C BDQ60 BDQ60 T C Dual Function BDQ60 BDQ60 BDQ60 Differential C T C 4-212 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number VCCIO AF26 AE25 GNDIO AD24 AE24 AD18 AC18 AE18 AG19 VCCIO GNDIO AC19 AD20 AB18 AC20 AE20 AE21 VCCIO AC23 AD23 GNDIO AH18 AK19 AJ18 AJ19 AH21 AK22 AK21 AJ22 AH22 AJ23 AH23 AK23 AH19 AJ20 AH20 AK20 AH24 AG24 AF24 AJ24 AK28 Ball/Pad Function VCCIO4 PB82A PB82B GNDIO4 PB92A PB92B PB93A PB93B PB94A PB94B VCCIO4 GNDIO4 PB96A PB96B PB97A PB97B PB98A PB98B VCCIO4 PB99A PB99B GNDIO4 LRC_SQ_VCCRX3 LRC_SQ_HDINP3 LRC_SQ_VCCIB3 LRC_SQ_HDINN3 LRC_SQ_VCCTX3 LRC_SQ_HDOUTP3 LRC_SQ_VCCOB3 LRC_SQ_HDOUTN3 LRC_SQ_VCCTX2 LRC_SQ_HDOUTN2 LRC_SQ_VCCOB2 LRC_SQ_HDOUTP2 LRC_SQ_VCCRX2 LRC_SQ_HDINN2 LRC_SQ_VCCIB2 LRC_SQ_HDINP2 LRC_SQ_VCCP LRC_SQ_REFCLKP LRC_SQ_REFCLKN LRC_SQ_VCCAUX33 LRC_SQ_HDINP1 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 T T C T C T C C T C T BDQ96 BDQ96 T C BDQS96 BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 T C T C T C BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 T C T C T C BDQ78 BDQ78 T C Dual Function Differential 4-213 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number AH28 AJ28 AH29 AK25 AH25 AJ25 AH26 AJ26 AK27 AK26 AH27 AJ29 AJ30 AK29 AH30 AG27 AD25 AG28 AG30 AG29 AC24 AF27 GNDIO AF28 AE26 AB23 AF29 VCCIO AF30 AD26 AE29 GNDIO AE30 AD29 AC25 AD30 VCCIO AA22 AC26 AA23 AB22 AC27 GNDIO Ball/Pad Function LRC_SQ_VCCIB1 LRC_SQ_HDINN1 LRC_SQ_VCCRX1 LRC_SQ_HDOUTP1 LRC_SQ_VCCOB1 LRC_SQ_HDOUTN1 LRC_SQ_VCCTX1 LRC_SQ_HDOUTN0 LRC_SQ_VCCOB0 LRC_SQ_HDOUTP0 LRC_SQ_VCCTX0 LRC_SQ_HDINN0 LRC_SQ_VCCIB0 LRC_SQ_HDINP0 LRC_SQ_VCCRX0 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** VCCIO8 D1*** D2*** D3*** GNDIO8 D4*** D5*** D6*** D7*** VCCIO8 DI/CSSPI0N*** DOUT/CSON/CSSPI1N*** BUSY/SISPI*** RLM0_PLLCAP PR102B GNDIO3 Bank 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 RLM0_GDLLC_FB_A/RDQ99 C T C T C C T C Dual Function Differential 4-214 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number AC28 AC29 AC30 AB30 VCCIO AA30 AB29 AB28 GNDIO Y22 Y23 AB26 AB27 VCCIO Y24 Y25 AA29 Y28 Y30 Y29 GNDIO VCCIO W22 V22 Y27 VCCIO Y26 W30 W29 GNDIO W25 W26 U29 V29 VCCIO V30 U30 W27 W28 V24 V25 GNDIO U28 Ball/Pad Function PR102A PR101B PR101A PR100B VCCIO3 PR100A PR99B PR99A GNDIO3 PR98B PR98A PR97B PR97A VCCIO3 PR96B PR96A PR95B PR95A PR93B PR93A GNDIO3 VCCIO3 PR83B PR83A PR82B VCCIO3 PR82A PR81B PR81A GNDIO3 PR80B PR80A PR79B PR79A VCCIO3 PR78B PR78A PR77B PR77A PR75B PR75A GNDIO3 PR74B Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ72 C (LVDS)* RDQ81 RDQ81 RDQ81 RDQ81 RDQ72 RDQ72 C T C (LVDS)* T (LVDS)* C T RDQ81 RDQ81 RDQ81 RDQ81 C T C (LVDS)* T (LVDS)* RDQ81 RDQ81 RDQS81 T C (LVDS)* T (LVDS)* RDQ81 RDQ81 RDQ81 C (LVDS)* T (LVDS)* C RDQ99 RDQ99 RDQ99 RDQ99 RDQ90 RDQ90 C T C (LVDS)* T (LVDS)* C T RDQ99 RDQ99 RDQ99 RDQ99 C T C (LVDS)* T (LVDS)* RLM0_GPLLT_IN_A**/RDQ99 RLM0_GPLLC_FB_A/RDQ99 RLM0_GPLLT_FB_A/RDQS99 T C (LVDS)* T (LVDS)* Dual Function RLM0_GDLLT_FB_A/RDQ99 RLM0_GDLLC_IN_A**/RDQ99 RLM0_GDLLT_IN_A**/RDQ99 RLM0_GPLLC_IN_A**/RDQ99 Differential T C (LVDS)* T (LVDS)* C 4-215 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number U27 U23 V23 VCCIO V26 U26 U25 GNDIO U24 T30 R30 T23 VCCIO T22 T29 T28 R23 GNDIO R22 P30 R29 T27 VCCIO T26 GNDIO N30 N29 VCCIO R27 R28 P29 P28 M30 M29 GNDIO P23 P24 R26 P27 VCCIO P25 P26 Ball/Pad Function PR74A PR73B PR73A VCCIO3 PR72B PR72A PR71B GNDIO3 PR71A PR70B PR70A PR69B VCCIO3 PR69A PR68B PR68A PR66B GNDIO3 PR66A PR65B PR65A PR64B VCCIO3 PR64A GNDIO3 PR61B PR61A VCCIO3 PR60B PR60A PR59B PR59A PR57B PR57A GNDIO2 PR56B PR56A PR55B PR55A VCCIO2 PR54B PR54A Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 RDQ54 RDQS54 C (LVDS)* T (LVDS)* RDQ54 RDQ54 RDQ54 RDQ54 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ63 VREF1_3/RDQ63 PCLKC3_0/RDQ63 PCLKT3_0/RDQ63 PCLKC2_0/RDQ54 PCLKT2_0/RDQ54 C T C (LVDS)* T (LVDS)* C T RDQ63 RDQ63 C (LVDS)* T (LVDS)* RDQ63 T RLM4_SPLLT_FB_A/RDQ63 RLM4_SPLLC_IN_A/RDQ63 RLM4_SPLLT_IN_A/RDQ63 RDQ63 T C (LVDS)* T (LVDS)* C RDQ72 RDQ72 RDQ72 RLM4_SPLLC_FB_A/RDQ63 T C (LVDS)* T (LVDS)* C RDQ72 RDQ72 RDQ72 RDQ72 T C (LVDS)* T (LVDS)* C RDQ72 RDQS72 RDQ72 C (LVDS)* T (LVDS)* C Dual Function RDQ72 RDQ72 RDQ72 Differential T (LVDS)* C T 4-216 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number K30 GNDIO K29 N22 P22 J30 VCCIO J29 N24 N23 N25 N26 GNDIO M27 M28 H30 G30 VCCIO M25 M26 L30 GNDIO L29 L28 L27 H29 VCCIO G29 L22 M22 F30 GNDIO F29 VCCIO GNDIO E30 E29 L25 L26 VCCIO H28 J28 Ball/Pad Function PR53B GNDIO2 PR53A PR52B PR52A PR51B VCCIO2 PR51A PR50B PR50A PR48B PR48A GNDIO2 PR47B PR47A PR46B PR46A VCCIO2 PR45B PR45A PR44B GNDIO2 PR44A PR43B PR43A PR42B VCCIO2 PR42A PR41B PR41A PR40B GNDIO2 PR40A VCCIO2 GNDIO2 PR34B PR34A PR33B PR33A VCCIO2 PR32B PR32A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ32 RDQS32 C (LVDS)* T (LVDS)* RDQ32 RDQ32 C T RDQ32 RDQ32 C (LVDS)* T (LVDS)* T RDQ45 RDQ45 RDQ45 T C (LVDS)* T (LVDS)* C RDQ45 RDQ45 RDQ45 RDQ45 T C (LVDS)* T (LVDS)* C RDQ45 RDQS45 RDQ45 C (LVDS)* T (LVDS)* C RDQ45 RDQ45 RDQ45 RDQ45 C (LVDS)* T (LVDS)* C T RUM3_SPLLT_FB_A/RDQ54 RUM3_SPLLC_IN_A/RDQ54 RUM3_SPLLT_IN_A/RDQ54 RDQ45 RDQ45 T C (LVDS)* T (LVDS)* C T RDQ54 RDQ54 RDQ54 RUM3_SPLLC_FB_A/RDQ54 T C (LVDS)* T (LVDS)* C Dual Function RDQ54 Differential C 4-217 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number G28 GNDIO G27 L24 L23 D30 VCCIO D29 K24 K25 J27 GNDIO K26 K23 K22 J22 VCCIO J23 GNDIO VCCIO J26 H26 H27 G26 VCCIO H23 H24 D28 GNDIO E28 G24 H25 D27 VCCIO E27 F26 G25 F24 GNDIO F25 VCCIO G23 Ball/Pad Function PR31B GNDIO2 PR31A PR30B PR30A PR29B VCCIO2 PR29A PR28B PR28A PR26B GNDIO2 PR26A PR25B PR25A PR24B VCCIO2 PR24A GNDIO2 VCCIO2 PR17B PR17A PR16B PR16A VCCIO2 PR15B PR15A PR14B GNDIO2 PR14A PR13B PR13A PR12B VCCIO2 PR12A PR11B PR11A PR9B GNDIO2 PR9A VCCIO2 XRES Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 VREF1_2 T RUM0_SPLLT_FB_A/RDQ15 RUM0_SPLLC_IN_A/RDQ15 RUM0_SPLLT_IN_A/RDQ15 VREF2_2 T C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 RUM0_SPLLC_FB_A/RDQ15 T C (LVDS)* T (LVDS)* C RDQ15 RDQS15 RDQ15 C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 RDQ15 C (LVDS)* T (LVDS)* C T RDQ23 T RDQ23 RDQ23 RDQ23 RDQ23 T C (LVDS)* T (LVDS)* C RDQ32 RDQ32 RDQ32 RDQ23 T C (LVDS)* T (LVDS)* C RDQ32 RDQ32 RDQ32 RDQ32 T C (LVDS)* T (LVDS)* C Dual Function RDQ32 Differential C 4-218 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number C30 A29 B30 B29 C27 A26 A27 B26 C26 B25 C25 A25 C29 B28 C28 A28 B24 E24 D24 C24 A20 C20 B20 C19 A23 C23 B23 C22 B22 A21 A22 C21 B19 B18 A19 C18 D23 GNDIO E21 D26 E26 E23 VCCIO Ball/Pad Function URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 PT100B GNDIO1 PT100A PT99B PT99A PT98B VCCIO1 Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 T C T C C T C T C C T C T C T T C T C C T C T Dual Function Differential 4-219 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number G22 D22 F21 G18 H18 D20 GNDIO D21 E20 VCCIO E19 D19 E18 D18 C17 A17 B17 GNDIO VCCIO J18 J19 H17 J17 F18 F17 GNDIO A16 B16 G17 G16 VCCIO H16 F16 J16 G15 GNDIO C16 D16 J15 H15 VCCIO A15 Ball/Pad Function PT98A PT97B PT97A PT96B PT96A PT95B GNDIO1 PT95A PT94B VCCIO1 PT94A PT93B PT93A PT92B PT92A PT91B PT91A GNDIO1 VCCIO1 PT75B PT75A PT74B PT74A PT73B PT73A GNDIO1 PT72B PT72A PT71B PT71A VCCIO1 PT70B PT70A PT69B PT69A GNDIO1 PT68B PT68A PT67B PT67A VCCIO1 PT66B Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VREF2_1 C C T C T C T C T C T C T C T C T C T T C T C T C T T C C T C T C Dual Function Differential T 4-220 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number B15 F15 E16 C15 GNDIO D15 C14 E15 G14 VCCIO J14 F14 H14 A14 B14 D13 GNDIO F13 G13 VCCIO J11 D4 D5 E5 F6 GNDIO VCCIO F7 D8 GNDIO J13 G11 H13 H12 VCCIO E8 D9 D12 GNDIO E13 VCCIO GNDIO J12 Ball/Pad Function PT66A PT65B PT65A PT64B GNDIO0 PT64A PT63B PT63A PT62B VCCIO0 PT62A PT61B PT61A PT60B PT60A PT59B GNDIO0 PT59A PT58B VCCIO0 PT58A PT57B PT56A PT55B PT55A GNDIO0 VCCIO0 PT52B PT52A GNDIO0 PT50B PT50A PT49B PT49A VCCIO0 PT48B PT48A PT46B GNDIO0 PT46A VCCIO0 GNDIO0 PT31B Bank 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C C T C T C T C T T T C T C T C T C PCLKT0_0 VREF2_0 VREF1_0 T C T C Dual Function VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 Differential T C T C 4-221 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number VCCIO H10 E12 D11 H11 F11 C13 A12 B13 B12 C10 A9 A10 B9 C9 B8 C8 A8 C12 B11 C11 A11 B7 E7 D7 C7 A3 C3 B3 C2 A6 C6 B6 C5 B5 A4 A5 C4 B2 B1 A2 C1 Ball/Pad Function VCCIO0 PT31A PT30B PT30A PT29B PT29A ULC_SQ_VCCRX0 ULC_SQ_HDINP0 ULC_SQ_VCCIB0 ULC_SQ_HDINN0 ULC_SQ_VCCTX0 ULC_SQ_HDOUTP0 ULC_SQ_VCCOB0 ULC_SQ_HDOUTN0 ULC_SQ_VCCTX1 ULC_SQ_HDOUTN1 ULC_SQ_VCCOB1 ULC_SQ_HDOUTP1 ULC_SQ_VCCRX1 ULC_SQ_HDINN1 ULC_SQ_VCCIB1 ULC_SQ_HDINP1 ULC_SQ_VCCAUX33 ULC_SQ_REFCLKN ULC_SQ_REFCLKP ULC_SQ_VCCP ULC_SQ_HDINP2 ULC_SQ_VCCIB2 ULC_SQ_HDINN2 ULC_SQ_VCCRX2 ULC_SQ_HDOUTP2 ULC_SQ_VCCOB2 ULC_SQ_HDOUTN2 ULC_SQ_VCCTX2 ULC_SQ_HDOUTN3 ULC_SQ_VCCOB3 ULC_SQ_HDOUTP3 ULC_SQ_VCCTX3 ULC_SQ_HDINN3 ULC_SQ_VCCIB3 ULC_SQ_HDINP3 ULC_SQ_VCCRX3 Bank 0 0 0 0 0 0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 T C T C C T C T C T T C T C C T C T T C T C T Dual Function Differential 4-222 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number L12 L13 L18 L19 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 N11 N12 N19 N20 P12 P19 R12 R19 T12 T19 U12 U19 V11 V12 V19 V20 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y12 Y13 Y18 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Bank Dual Function Differential 4-223 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number Y19 D14 E6 E9 F12 K12 K13 D17 E22 E25 F19 K18 K19 F28 J25 K28 M21 M24 N21 N28 P21 R25 AA28 AB25 AE28 T25 U21 V21 V28 W21 W24 AA18 AA19 AE19 AF22 AG17 AG25 AA12 AA13 AE12 AF9 AG14 AG6 Ball/Pad Function VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 Bank 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 Dual Function Differential 4-224 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number AA3 AB6 AE3 T6 U10 V10 V3 W10 W7 F3 J6 K3 M10 M7 N10 N3 P10 R6 AA25 AD28 AA10 AA11 AA20 AA21 K10 K11 K20 K21 L10 L11 L20 L21 Y10 Y11 Y20 Y21 A1 A13 A18 A24 A30 A7 AA14 Ball/Pad Function VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND Bank 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 Dual Function Differential 4-225 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number AA15 AA16 AA17 AA24 AA27 AA4 AB24 AB7 AD12 AD19 AD27 AE22 AE27 AE4 AE9 AF14 AF17 AF25 AF6 AJ10 AJ21 AJ27 AJ4 AK1 AK13 AK18 AK24 AK30 AK7 B10 B21 B27 B4 D25 D6 E14 E17 F22 F27 F4 F9 G12 G19 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential 4-226 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number J24 J7 K14 K15 K16 K17 K27 K4 L14 L15 L16 L17 M23 M8 N14 N15 N16 N17 N27 N4 P11 P13 P14 P15 P16 P17 P18 P20 R10 R11 R13 R14 R15 R16 R17 R18 R20 R21 R24 R7 T10 T11 T13 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential 4-227 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number T14 T15 T16 T17 T18 T20 T21 T24 T7 U11 U13 U14 U15 U16 U17 U18 U20 V14 V15 V16 V17 V27 V4 W23 W8 Y14 Y15 Y16 Y17 AA26 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB19 AB20 AB21 AB9 AC10 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential 4-228 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number AC11 AC21 AC22 AC8 AC9 AD21 AD22 AD4 AD5 AD6 AD7 AD8 AE23 AE5 AE6 AE7 AF20 AF23 AF5 AG23 AG26 D10 E10 E11 F10 F20 F23 F8 G10 G20 G21 G7 G8 G9 H19 H20 H21 H22 H6 H8 H9 J10 J20 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential 4-229 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.) LFE2M100E/SE Ball Number J21 J9 K9 R9 U22 W9 N13 N18 V13 V18 Ball/Pad Function NC NC NC NC NC NC VCCPLL VCCPLL VCCPLL VCCPLL Bank Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation. ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-230 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number VCCIO F4 F3 GNDIO E1 E2 K9 H7 VCCIO F1 F2 J8 H6 GNDIO G2 G1 J7 VCCIO L8 L9 L10 H5 GNDIO J6 H2 H1 G5 G6 M9 M10 H3 H4 J2 J1 K2 K1 VCCIO J4 J3 J5 K5 GNDIO L2 L1 L7 K6 VCCIO M2 Ball/Pad Function VCCIO7 PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B VCCIO7 PL13A PL13B PL14A PL14B GNDIO7 PL15A PL15B PL16A VCCIO7 PL16B PL17A PL17B PL18A GNDIO7 PL18B NC NC NC NC NC NC NC NC PL19A PL19B PL20A PL20B VCCIO7 PL21A PL21B PL22A PL22B GNDIO7 PL24A PL24B PL25A PL25B VCCIO7 PL26A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ28 T (LVDS)* LDQ28 LDQ28 LDQ28 LDQ28 T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C C (LVDS)* T C T (LVDS)* LDQ15 C LDQ15 LDQ15 LDQ15 LDQ15 C T (LVDS)* C (LVDS)* T LDQS15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T LDQ15 LDQ15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T C LUM0_SPLLT_IN_A/LDQ15 LUM0_SPLLC_IN_A/LDQ15 LUM0_SPLLT_FB_A/LDQ15 LUM0_SPLLC_FB_A/LDQ15 T (LVDS)* C (LVDS)* T C VREF2_7 VREF1_7 T C Dual Function Differential Ball/Pad Function VCCIO7 PL9A PL9B GNDIO7 PL11A PL11B PL12A PL12B VCCIO7 PL13A PL13B PL14A PL14B GNDIO7 PL15A PL15B PL16A VCCIO7 PL16B PL17A PL17B PL18A GNDIO7 PL18B PL19A PL19B PL20A PL20B PL21A VCCIO7 PL21B PL22A PL22B PL23A GNDIO7 PL23B PL24A PL24B VCCIO7 PL25A PL25B PL26A PL26B GNDIO7 PL28A PL28B PL29A PL29B VCCIO7 PL30A LFE2M100E/SE Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ32 T (LVDS)* LDQ32 LDQ32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T C LDQ23 LDQ23 LDQ23 LDQ23 T (LVDS)* C (LVDS)* T C LDQ23 LDQ23 LDQ23 C (LVDS)* T C LDQ23 LDQ23 LDQ23 LDQS23 C (LVDS)* T C T (LVDS)* LDQ15 LDQ23 LDQ23 LDQ23 LDQ23 LDQ23 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ15 LDQ15 LDQ15 LDQ15 C T (LVDS)* C (LVDS)* T LDQS15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T LDQ15 LDQ15 LDQ15 LDQ15 T (LVDS)* C (LVDS)* T C LUM0_SPLLT_IN_A/LDQ15 LUM0_SPLLC_IN_A/LDQ15 LUM0_SPLLT_FB_A/LDQ15 LUM0_SPLLC_FB_A/LDQ15 T (LVDS)* C (LVDS)* T C VREF2_7 VREF1_7 T C Dual Function Differential 4-231 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number M1 L6 L5 GNDIO L3 L4 M3 VCCIO M4 N1 N2 M5 GNDIO N6 P3 P4 P9 M7 P1 P2 N7 P7 P5 N5 P8 P6 VCCIO R3 R4 R10 P11 GNDIO R7 R8 R5 VCCIO T5 R1 R2 R11 GNDIO T10 T1 T2 U10 U8 VCCIO T6 Ball/Pad Function PL26B PL27A PL27B GNDIO7 PL28A PL28B PL29A VCCIO7 PL29B PL30A PL30B PL31A GNDIO7 PL31B NC NC NC NC NC NC NC NC PL33A PL33B PL34A PL34B VCCIO7 PL35A PL35B PL36A PL36B GNDIO7 PL37A PL37B PL38A VCCIO7 PL38B PL39A PL39B PL40A GNDIO7 PL40B PL42A PL42B PL43A PL43B VCCIO7 PL44A Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ46 T (LVDS)* LDQ37 LUM3_SPLLT_IN_A/LDQ46 LUM3_SPLLC_IN_A/LDQ46 LUM3_SPLLT_FB_A/LDQ46 LUM3_SPLLC_FB_A/LDQ46 C T (LVDS)* C (LVDS)* T C LDQ37 LDQ37 LDQ37 LDQ37 C T (LVDS)* C (LVDS)* T LDQS37 LDQ37 LDQ37 T (LVDS)* C (LVDS)* T LDQ37 LDQ37 LDQ37 LDQ37 T (LVDS)* C (LVDS)* T C LDQ37 LDQ37 LDQ37 LDQ37 T (LVDS)* C (LVDS)* T C LDQ28 C LDQ28 LDQ28 LDQ28 LDQ28 C T (LVDS)* C (LVDS)* T LDQS28 LDQ28 LDQ28 T (LVDS)* C (LVDS)* T Dual Function LDQ28 LDQ28 LDQ28 Differential C (LVDS)* T C Ball/Pad Function PL30B PL31A PL31B GNDIO7 PL32A PL32B PL33A VCCIO7 PL33B PL34A PL34B PL35A GNDIO7 PL35B PL37A GNDIO7 PL37B PL38A PL38B VCCIO7 PL39A PL39B PL40A PL40B GNDIO7 PL41A PL41B PL42A PL42B VCCIO7 PL43A PL43B PL44A PL44B GNDIO7 PL45A PL45B PL46A VCCIO7 PL46B PL47A PL47B PL48A GNDIO7 PL48B PL50A PL50B PL51A PL51B VCCIO7 PL52A LFE2M100E/SE Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LDQ54 T (LVDS)* LDQ45 LUM3_SPLLT_IN_A/LDQ54 LUM3_SPLLC_IN_A/LDQ54 LUM3_SPLLT_FB_A/LDQ54 LUM3_SPLLC_FB_A/LDQ54 C T (LVDS)* C (LVDS)* T C LDQ45 LDQ45 LDQ45 LDQ45 C T (LVDS)* C (LVDS)* T LDQS45 LDQ45 LDQ45 T (LVDS)* C (LVDS)* T LDQ45 LDQ45 LDQ45 LDQ45 T (LVDS)* C (LVDS)* T C LDQ45 LDQ45 LDQ45 LDQ45 T (LVDS)* C (LVDS)* T C T (LVDS)* C (LVDS)* T C C (LVDS)* T C LDQ32 C T (LVDS)* LDQ32 LDQ32 LDQ32 LDQ32 C T (LVDS)* C (LVDS)* T LDQS32 LDQ32 LDQ32 T (LVDS)* C (LVDS)* T Dual Function LDQ32 LDQ32 LDQ32 Differential C (LVDS)* T C 4-232 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number R6 U9 T7 GNDIO U5 U6 U7 VCCIO V9 V11 V10 U4 GNDIO U3 U2 U1 V5 V6 V7 VCCIO V8 V4 V3 V2 GNDIO V1 W7 W5 VCCIO W2 W1 Y6 W6 GNDIO Y1 Y2 Y7 Y5 VCCIO W10 Y8 Y4 Y3 GNDIO AA1 AA2 AA8 VCCIO Y9 AA6 AA7 Ball/Pad Function PL44B PL45A PL45B GNDIO7 PL46A PL46B PL47A VCCIO7 PL47B PL48A PL48B PL49A GNDIO7 PL49B PL51A PL51B PL52A PL52B PL53A VCCIO6 PL53B PL54A PL54B PL55A GNDIO6 PL55B PL56A PL56B VCCIO6 PL57A PL57B PL58A PL58B GNDIO6 PL60A PL60B PL61A PL61B VCCIO6 PL62A PL62B PL63A PL63B GNDIO6 PL64A PL64B PL65A VCCIO6 PL65B PL66A PL66B Bank 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ64 LDQ64 LDQ64 C T (LVDS)* C (LVDS)* LDQS64 LDQ64 LDQ64 T (LVDS)* C (LVDS)* T LDQ64 LDQ64 LDQ64 LDQ64 T (LVDS)* C (LVDS)* T C LDQ64 LDQ64 LDQ64 LDQ64 T (LVDS)* C (LVDS)* T C LLM3_SPLLT_IN_A/LDQ55 LLM3_SPLLC_IN_A/LDQ55 LLM3_SPLLT_FB_A/LDQ55 LLM3_SPLLC_FB_A/LDQ55 T (LVDS)* C (LVDS)* T C LDQ55 LDQ55 LDQ55 C (LVDS)* T C LDQ55 LDQ55 LDQ55 LDQS55 C (LVDS)* T C T (LVDS)* PCLKC7_0/LDQ46 PCLKT6_0/LDQ55 PCLKC6_0/LDQ55 VREF2_6/LDQ55 VREF1_6/LDQ55 LDQ55 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ46 LDQ46 LDQ46 PCLKT7_0/LDQ46 C T (LVDS)* C (LVDS)* T LDQS46 LDQ46 LDQ46 T (LVDS)* C (LVDS)* T Dual Function LDQ46 LDQ46 LDQ46 Differential C (LVDS)* T C Ball/Pad Function PL52B PL53A PL53B GNDIO7 PL54A PL54B PL55A VCCIO7 PL55B PL56A PL56B PL57A GNDIO7 PL57B PL59A PL59B PL60A PL60B PL61A VCCIO6 PL61B PL62A PL62B PL63A GNDIO6 PL63B PL64A PL64B VCCIO6 PL65A PL65B PL66A PL66B GNDIO6 PL68A PL68B PL69A PL69B VCCIO6 PL70A PL70B PL71A PL71B GNDIO6 PL72A PL72B PL73A VCCIO6 PL73B PL74A PL74B LFE2M100E/SE Bank 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ72 LDQ72 LDQ72 C T (LVDS)* C (LVDS)* LDQS72 LDQ72 LDQ72 T (LVDS)* C (LVDS)* T LDQ72 LDQ72 LDQ72 LDQ72 T (LVDS)* C (LVDS)* T C LDQ72 LDQ72 LDQ72 LDQ72 T (LVDS)* C (LVDS)* T C LLM4_SPLLT_IN_A/LDQ63 LLM4_SPLLC_IN_A/LDQ63 LLM4_SPLLT_FB_A/LDQ63 LLM4_SPLLC_FB_A/LDQ63 T (LVDS)* C (LVDS)* T C LDQ63 LDQ63 LDQ63 C (LVDS)* T C LDQ63 LDQ63 LDQ63 LDQS63 C (LVDS)* T C T (LVDS)* PCLKC7_0/LDQ54 PCLKT6_0/LDQ63 PCLKC6_0/LDQ63 VREF2_6/LDQ63 VREF1_6/LDQ63 LDQ63 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ54 LDQ54 LDQ54 PCLKT7_0/LDQ54 C T (LVDS)* C (LVDS)* T LDQS54 LDQ54 LDQ54 T (LVDS)* C (LVDS)* T Dual Function LDQ54 LDQ54 LDQ54 Differential C (LVDS)* T C 4-233 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AA4 GNDIO AA3 AA9 AA10 AA5 AB6 AB1 VCCIO AB2 AC8 AB10 AC1 GNDIO AC2 AB7 AB5 VCCIO AC3 AC4 AC10 AC9 GNDIO AC7 AC5 AC6 AD5 AD4 AD3 AD10 AD8 AD2 AD1 AD9 AC11 AD6 AD7 AE1 AE2 AF2 AF1 AE5 AE6 AF4 VCCIO AF3 AF5 Ball/Pad Function PL67A GNDIO6 PL67B PL69A PL69B PL70A PL70B PL71A VCCIO6 PL71B PL72A PL72B PL73A GNDIO6 PL73B PL74A PL74B VCCIO6 PL75A PL75B PL76A PL76B GNDIO6 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PL78A PL78B PL79A PL79B PL80A VCCIO6 PL80B PL81A Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ82 LDQ82 C (LVDS)* T LDQ82 LDQ82 LDQ82 LDQ82 LDQ82 T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ73 LDQ73 LDQ73 LDQ73 T (LVDS)* C (LVDS)* T C LDQ73 LDQ73 LDQ73 C (LVDS)* T C LDQ73 LDQ73 LDQ73 LDQS73 C (LVDS)* T C T (LVDS)* LDQ64 LDQ73 LDQ73 LDQ73 LDQ73 LDQ73 C T (LVDS)* C (LVDS)* T C T (LVDS)* Dual Function LDQ64 Differential T Ball/Pad Function PL75A GNDIO6 PL75B PL77A PL77B PL78A PL78B PL79A VCCIO6 PL79B PL80A PL80B PL81A GNDIO6 PL81B PL82A PL82B VCCIO6 PL83A PL83B PL84A PL84B GNDIO6 PL86A PL86B PL87A PL87B VCCIO6 PL88A PL88B PL89A PL89B GNDIO6 PL90A PL90B PL91A VCCIO6 PL91B PL92A PL92B PL93A GNDIO6 PL93B PL95A PL95B PL96A PL96B PL97A VCCIO6 PL97B PL98A LFE2M100E/SE Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LDQ99 LDQ99 C (LVDS)* T LDQ90 LDQ99 LDQ99 LDQ99 LDQ99 LDQ99 C T (LVDS)* C (LVDS)* T C T (LVDS)* LDQ90 LDQ90 LDQ90 LDQ90 C T (LVDS)* C (LVDS)* T LDQS90 LDQ90 LDQ90 T (LVDS)* C (LVDS)* T LDQ90 LDQ90 LDQ90 LDQ90 T (LVDS)* C (LVDS)* T C LDQ90 LDQ90 LDQ90 LDQ90 T (LVDS)* C (LVDS)* T C LDQ81 LDQ81 LDQ81 LDQ81 T (LVDS)* C (LVDS)* T C LDQ81 LDQ81 LDQ81 C (LVDS)* T C LDQ81 LDQ81 LDQ81 LDQS81 C (LVDS)* T C T (LVDS)* LDQ72 LDQ81 LDQ81 LDQ81 LDQ81 LDQ81 C T (LVDS)* C (LVDS)* T C T (LVDS)* Dual Function LDQ72 Differential T 4-234 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AF6 AG1 GNDIO AG2 AE9 AF7 VCCIO AH1 AH2 AG5 AG4 GNDIO AG6 AJ1 AJ2 AK2 AK1 AL1 AF10 AK3 AN2 AM2 AN1 AM3 AN3 AP2 AM1 AP3 AN4 AP4 AL3 AP5 AN5 AM4 AL4 AM5 AL6 AL5 AK5 AK6 AM6 AL8 AM7 AN6 AP6 AK7 AP7 AN7 AP8 Ball/Pad Function PL81B PL82A GNDIO6 PL82B PL83A PL83B VCCIO6 PL84A PL84B PL85A PL85B GNDIO6 LLM0_PLLCAP PL87A PL87B TCK TDI TMS TDO VCCJ LLC_SQ_VCCRX3 LLC_SQ_HDINP3 LLC_SQ_VCCIB3 LLC_SQ_HDINN3 LLC_SQ_VCCTX3 LLC_SQ_HDOUTP3 LLC_SQ_VCCOB3 LLC_SQ_HDOUTN3 LLC_SQ_VCCTX2 LLC_SQ_HDOUTN2 LLC_SQ_VCCOB2 LLC_SQ_HDOUTP2 LLC_SQ_VCCRX2 LLC_SQ_HDINN2 LLC_SQ_VCCIB2 LLC_SQ_HDINP2 LLC_SQ_VCCP LLC_SQ_REFCLKP LLC_SQ_REFCLKN LLC_SQ_VCCAUX33 LLC_SQ_HDINP1 LLC_SQ_VCCIB1 LLC_SQ_HDINN1 LLC_SQ_VCCRX1 LLC_SQ_HDOUTP1 LLC_SQ_VCCOB1 LLC_SQ_HDOUTN1 LLC_SQ_VCCTX1 LLC_SQ_HDOUTN0 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 C C T C T T C T C T C C T C T T C LLM0_GDLLT_IN_A**/LDQ82 LLM0_GDLLC_IN_A**/LDQ82 LLM0_GDLLT_FB_A/LDQ82 LLM0_GDLLC_FB_A/LDQ82 T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A**/LDQ82 LLM0_GPLLT_FB_A/LDQ82 LLM0_GPLLC_FB_A/LDQ82 C (LVDS)* T C Dual Function LDQ82 LLM0_GPLLT_IN_A**/LDQS82 Differential C T (LVDS)* Ball/Pad Function PL98B PL99A GNDIO6 PL99B PL100A PL100B VCCIO6 PL101A PL101B PL102A PL102B GNDIO6 LLM0_PLLCAP PL104A PL104B TCK TDI TMS TDO VCCJ LLC_SQ_VCCRX3 LLC_SQ_HDINP3 LLC_SQ_VCCIB3 LLC_SQ_HDINN3 LLC_SQ_VCCTX3 LLC_SQ_HDOUTP3 LLC_SQ_VCCOB3 LLC_SQ_HDOUTN3 LLC_SQ_VCCTX2 LLC_SQ_HDOUTN2 LLC_SQ_VCCOB2 LLC_SQ_HDOUTP2 LLC_SQ_VCCRX2 LLC_SQ_HDINN2 LLC_SQ_VCCIB2 LLC_SQ_HDINP2 LLC_SQ_VCCP LLC_SQ_REFCLKP LLC_SQ_REFCLKN LLC_SQ_VCCAUX33 LLC_SQ_HDINP1 LLC_SQ_VCCIB1 LLC_SQ_HDINN1 LLC_SQ_VCCRX1 LLC_SQ_HDOUTP1 LLC_SQ_VCCOB1 LLC_SQ_HDOUTN1 LLC_SQ_VCCTX1 LLC_SQ_HDOUTN0 LFE2M100E/SE Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 C C T C T T C T C T C C T C T T C LLM0_GDLLT_IN_A**/LDQ99 LLM0_GDLLC_IN_A**/ LDQ99 LLM0_GDLLT_FB_A/LDQ99 LLM0_GDLLC_FB_A/LDQ99 T (LVDS)* C (LVDS)* T C LLM0_GPLLC_IN_A**/ LDQ99 LLM0_GPLLT_FB_A/LDQ99 LLM0_GPLLC_FB_A/LDQ99 C (LVDS)* T C Dual Function LDQ99 LLM0_GPLLT_IN_A**/ LDQS99 Differential C T (LVDS)* 4-235 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AL9 AP9 AN8 AM8 AN9 AM9 AL7 AJ12 AH12 AL13 AK13 AE14 AG13 AN14 AP14 AH14 AJ15 VCCIO GNDIO AL14 AM14 AF14 AF13 VCCIO AE15 AG14 AH15 AK15 GNDIO AL15 AM15 AK16 AJ16 AN15 VCCIO AP15 AG15 GNDIO AE16 AF15 VCCIO AD16 AK17 AH16 AN16 GNDIO AP16 Ball/Pad Function LLC_SQ_VCCOB0 LLC_SQ_HDOUTP0 LLC_SQ_VCCTX0 LLC_SQ_HDINN0 LLC_SQ_VCCIB0 LLC_SQ_HDINP0 LLC_SQ_VCCRX0 NC NC NC NC NC NC PB30A PB30B PB31A PB31B VCCIO5 GNDIO5 PB33A PB33B PB35A PB35B VCCIO5 PB36A PB36B PB37A PB37B GNDIO5 PB38A PB38B PB39A PB39B PB40A VCCIO5 PB40B PB42A GNDIO5 PB42B PB44A VCCIO5 PB44B PB45A PB45B PB46A GNDIO5 PB46B Bank 14 14 14 14 14 14 14 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ42 C BDQ42 BDQ42 BDQ42 BDQ42 C T C T BDQ42 BDQ42 C T BDQ42 BDQS42 C T BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 T C T C T BDQ33 BDQ33 BDQ33 BDQ33 T C T C BDQS33 BDQ33 BDQ33 BDQ33 T C T C BDQ33 BDQ33 BDQ33 BDQ33 T C T C T C T Dual Function Differential Ball/Pad Function LLC_SQ_VCCOB0 LLC_SQ_HDOUTP0 LLC_SQ_VCCTX0 LLC_SQ_HDINN0 LLC_SQ_VCCIB0 LLC_SQ_HDINP0 LLC_SQ_VCCRX0 VCCIO5 PB32A PB32B GNDIO5 VCCIO5 PB36A PB36B GNDIO5 PB38A PB38B PB39A PB39B PB40A PB40B VCCIO5 GNDIO5 PB42A PB42B PB44A PB44B VCCIO5 PB45A PB45B PB46A PB46B GNDIO5 PB47A PB47B PB48A PB48B PB49A VCCIO5 PB49B PB51A GNDIO5 PB51B PB53A VCCIO5 PB53B PB54A PB54B PB55A GNDIO5 PB55B LFE2M100E/SE Bank 14 14 14 14 14 14 14 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BDQ51 C BDQ51 BDQ51 BDQ51 BDQ51 C T C T BDQ51 BDQ51 C T BDQ51 BDQS51 C T BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 T C T C T BDQ42 BDQ42 BDQ42 BDQ42 T C T C BDQS42 BDQ42 BDQ42 BDQ42 T C T C BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 BDQ42 T C T C T C BDQ33 BDQ33 T C BDQ33 BDQ33 T C T C T Dual Function Differential 4-236 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AL17 AM17 AN17 AP17 AD17 AE17 VCCIO AL18 AM18 GNDIO AP18 AN18 AG17 AJ17 AF17 AH17 VCCIO GNDIO AF18 VCCIO AD18 AP19 AN19 AP20 GNDIO AM20 AN20 AM21 AG18 VCCIO AE18 AJ18 AH18 AK18 GNDIO AK19 AP21 AN21 AL20 AK20 AN22 AL21 VCCIO GNDIO AH19 AJ20 AD20 AF20 VCCIO AJ19 AH20 Ball/Pad Function PB47A PB47B PB48A PB48B PB49A PB49B VCCIO5 PB50A PB50B GNDIO5 PB51A PB51B PB52A PB52B PB53A PB53B VCCIO5 GNDIO5 PB58A VCCIO4 PB58B PB59A PB59B PB60A GNDIO4 PB60B PB61A PB61B PB62A VCCIO4 PB62B PB63A PB63B PB64A GNDIO4 PB64B PB65A PB65B PB66A PB66B PB67A PB67B VCCIO4 GNDIO4 PB69A PB69B PB71A PB71B VCCIO4 PB72A PB72B Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ69 BDQ69 T C BDQS69 BDQ69 BDQ69 BDQ69 T C T C BDQ60 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 BDQ69 C T C T C T C BDQ60 BDQ60 BDQ60 BDQ60 C T C T BDQ60 BDQ60 BDQ60 BDQ60 C T C T PCLKC4_0/BDQ60 VREF2_4/BDQ60 VREF1_4/BDQ60 BDQS60 C T C T PCLKT4_0/BDQ60 T BDQS51 BDQ51 VREF2_5/BDQ51 VREF1_5/BDQ51 PCLKT5_0/BDQ51 PCLKC5_0/BDQ51 T C T C T C BDQ51 BDQ51 T C Dual Function BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 BDQ51 Differential T C T C T C Ball/Pad Function PB56A PB56B PB57A PB57B PB58A PB58B VCCIO5 PB59A PB59B GNDIO5 PB60A PB60B PB61A PB61B PB62A PB62B VCCIO5 GNDIO5 PB67A VCCIO4 PB67B PB68A PB68B PB69A GNDIO4 PB69B PB70A PB70B PB71A VCCIO4 PB71B PB72A PB72B PB73A GNDIO4 PB73B PB74A PB74B PB75A PB75B PB76A PB76B VCCIO4 GNDIO4 PB78A PB78B PB80A PB80B VCCIO4 PB81A PB81B LFE2M100E/SE Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 BDQ78 BDQ78 T C BDQS78 BDQ78 BDQ78 BDQ78 T C T C BDQ69 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 C T C T C T C BDQ69 BDQ69 BDQ69 BDQ69 C T C T BDQ69 BDQ69 BDQ69 BDQ69 C T C T PCLKC4_0/BDQ69 VREF2_4/BDQ69 VREF1_4/BDQ69 BDQS69 C T C T PCLKT4_0/BDQ69 T BDQS60 BDQ60 VREF2_5/BDQ60 VREF1_5/BDQ60 PCLKT5_0/BDQ60 PCLKC5_0/BDQ60 T C T C T C BDQ60 BDQ60 T C Dual Function BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 BDQ60 Differential T C T C T C 4-237 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AE20 AG20 GNDIO AH22 AH21 AG22 AG21 AM22 AL22 VCCIO AP23 AN23 GNDIO AM24 AL24 AK22 AJ22 AL23 AK23 VCCIO AJ23 AH23 GNDIO AL28 AM26 AN26 AM27 AN27 AP26 AL26 AP27 AN28 AP28 AK28 AP29 AN29 AM28 AL27 AM29 AL29 AL30 AK30 AK29 AM30 AL31 AM31 AN30 AP30 AL32 Ball/Pad Function PB73A PB73B GNDIO4 NC NC NC NC PB74A PB74B VCCIO4 PB77A PB77B GNDIO4 PB78A PB78B PB79A PB79B PB80A PB80B VCCIO4 PB81A PB81B GNDIO4 LRC_SQ_VCCRX3 LRC_SQ_HDINP3 LRC_SQ_VCCIB3 LRC_SQ_HDINN3 LRC_SQ_VCCTX3 LRC_SQ_HDOUTP3 LRC_SQ_VCCOB3 LRC_SQ_HDOUTN3 LRC_SQ_VCCTX2 LRC_SQ_HDOUTN2 LRC_SQ_VCCOB2 LRC_SQ_HDOUTP2 LRC_SQ_VCCRX2 LRC_SQ_HDINN2 LRC_SQ_VCCIB2 LRC_SQ_HDINP2 LRC_SQ_VCCP LRC_SQ_REFCLKP LRC_SQ_REFCLKN LRC_SQ_VCCAUX33 LRC_SQ_HDINP1 LRC_SQ_VCCIB1 LRC_SQ_HDINN1 LRC_SQ_VCCRX1 LRC_SQ_HDOUTP1 LRC_SQ_VCCOB1 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 T C T T C T C T C C T C T BDQ78 BDQ78 T C BDQS78 BDQ78 BDQ78 BDQ78 BDQ78 BDQ78 T C T C T C BDQ78 BDQ78 T C BDQ78 BDQ78 T C Dual Function BDQ69 BDQ69 Differential T C Ball/Pad Function PB82A PB82B GNDIO4 PB89A VCCIO4 PB89B PB90A PB90B GNDIO4 PB92A PB92B VCCIO4 PB95A PB95B GNDIO4 PB96A PB96B PB97A PB97B PB98A PB98B VCCIO4 PB99A PB99B GNDIO4 LRC_SQ_VCCRX3 LRC_SQ_HDINP3 LRC_SQ_VCCIB3 LRC_SQ_HDINN3 LRC_SQ_VCCTX3 LRC_SQ_HDOUTP3 LRC_SQ_VCCOB3 LRC_SQ_HDOUTN3 LRC_SQ_VCCTX2 LRC_SQ_HDOUTN2 LRC_SQ_VCCOB2 LRC_SQ_HDOUTP2 LRC_SQ_VCCRX2 LRC_SQ_HDINN2 LRC_SQ_VCCIB2 LRC_SQ_HDINP2 LRC_SQ_VCCP LRC_SQ_REFCLKP LRC_SQ_REFCLKN LRC_SQ_VCCAUX33 LRC_SQ_HDINP1 LRC_SQ_VCCIB1 LRC_SQ_HDINN1 LRC_SQ_VCCRX1 LRC_SQ_HDOUTP1 LRC_SQ_VCCOB1 LFE2M100E/SE Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 T C T T C T C T C C T C T BDQ96 BDQ96 T C BDQS96 BDQ96 BDQ96 BDQ96 BDQ96 BDQ96 T C T C T C BDQ96 BDQ96 T C BDQ96 BDQ96 T C BDQ87 BDQ87 BDQ87 C T C BDQ87 T Dual Function BDQ78 BDQ78 Differential T C 4-238 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AP31 AN31 AP32 AM34 AP33 AN32 AM32 AN34 AM33 AN33 AH28 AD24 AJ29 AF25 AJ28 AE25 AK31 GNDIO AE24 AJ30 AD25 AG29 VCCIO AG28 AG30 AH29 GNDIO AF26 AH30 AE26 AJ31 VCCIO AG27 AK32 AK33 AF27 AF28 GNDIO AD26 AJ32 AJ33 AJ34 VCCIO AK34 AH33 AH34 GNDIO Ball/Pad Function LRC_SQ_HDOUTN1 LRC_SQ_VCCTX1 LRC_SQ_HDOUTN0 LRC_SQ_VCCOB0 LRC_SQ_HDOUTP0 LRC_SQ_VCCTX0 LRC_SQ_HDINN0 LRC_SQ_VCCIB0 LRC_SQ_HDINP0 LRC_SQ_VCCRX0 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** VCCIO8 D1*** D2*** D3*** GNDIO8 D4*** D5*** D6*** D7*** VCCIO8 DI/CSSPI0N*** DOUT/CSON/ CSSPI1N*** BUSY/SISPI*** RLM0_PLLCAP PR85B GNDIO3 PR85A PR84B PR84A PR83B VCCIO3 PR83A PR82B PR82A GNDIO3 Bank 13 13 13 13 13 13 13 13 13 13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 RLM0_GPLLT_IN_A** RLM0_GPLLC_FB_A RLM0_GPLLT_FB_A/RDQS82**** T C (LVDS)* T (LVDS)* RLM0_GDLLT_FB_A RLM0_GDLLC_IN_A** RLM0_GDLLT_IN_A** RLM0_GPLLC_IN_A** T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A C T C T C Dual Function Differential C Ball/Pad Function LRC_SQ_HDOUTN1 LRC_SQ_VCCTX1 LRC_SQ_HDOUTN0 LRC_SQ_VCCOB0 LRC_SQ_HDOUTP0 LRC_SQ_VCCTX0 LRC_SQ_HDINN0 LRC_SQ_VCCIB0 LRC_SQ_HDINP0 LRC_SQ_VCCRX0 CFG2 CFG1 CFG0 PROGRAMN CCLK INITN DONE GNDIO8 WRITEN*** CS1N*** CSN*** D0/SPIFASTN*** VCCIO8 D1*** D2*** D3*** GNDIO8 D4*** D5*** D6*** D7*** VCCIO8 DI/CSSPI0N*** DOUT/CSON/ CSSPI1N*** BUSY/SISPI*** RLM0_PLLCAP PR102B GNDIO3 PR102A PR101B PR101A PR100B VCCIO3 PR100A PR99B PR99A GNDIO3 LFE2M100E/SE Bank 13 13 13 13 13 13 13 13 13 13 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 RLM0_GPLLT_IN_A**/ RDQ99 RLM0_GPLLC_FB_A/RDQ99 RLM0_GPLLT_FB_A/ RDQS99 T C (LVDS)* T (LVDS)* RLM0_GDLLT_FB_A/RDQ99 RLM0_GDLLC_IN_A**/ RDQ99 RLM0_GDLLT_IN_A**/ RDQ99 RLM0_GPLLC_IN_A**/ RDQ99 T C (LVDS)* T (LVDS)* C RLM0_GDLLC_FB_A/RDQ99 C T C T C Dual Function Differential C 4-239 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AF29 AF31 AG33 AG34 VCCIO AF30 AF32 AE29 AE30 AF33 AF34 AC27 AC28 AD29 AD30 AE33 AE34 AD32 AD31 AB25 AC25 AB28 AA26 AD33 AD34 AC29 GNDIO AA27 AC32 AC31 AA25 VCCIO AC24 AC33 AC34 GNDIO AB24 Y26 AB33 AB34 VCCIO Y27 AB29 AA34 AA33 AA31 AA32 Ball/Pad Function PR81B PR81A PR80B PR80A VCCIO3 PR79B PR79A PR78B PR78A NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PR76B GNDIO3 PR76A PR75B PR75A PR74B VCCIO3 PR74A PR73B PR73A GNDIO3 PR72B PR72A PR71B PR71A VCCIO3 PR70B PR70A PR69B PR69A PR67B PR67A Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ73 RDQ73 RDQ73 RDQ73 RDQ64 RDQ64 C T C (LVDS)* T (LVDS)* C T RDQ73 RDQ73 RDQ73 RDQ73 C T C (LVDS)* T (LVDS)* RDQ73 RDQ73 RDQS73 T C (LVDS)* T (LVDS)* RDQ73 RDQ73 RDQ73 RDQ73 T C (LVDS)* T (LVDS)* C RDQ73 C RDQ82 RDQ82 RDQ82 RDQ82 C T C (LVDS)* T (LVDS)* Dual Function RDQ82 RDQ82 RDQ82 RDQ82 Differential C T C (LVDS)* T (LVDS)* Ball/Pad Function PR98B PR98A PR97B PR97A VCCIO3 PR96B PR96A PR95B PR95A PR93B PR93A GNDIO3 PR92B PR92A PR91B PR91A VCCIO3 PR90B PR90A PR89B GNDIO3 PR89A PR88B PR88A PR87B VCCIO3 PR87A PR86B PR86A PR84B GNDIO3 PR84A PR83B PR83A PR82B VCCIO3 PR82A PR81B PR81A GNDIO3 PR80B PR80A PR79B PR79A VCCIO3 PR78B PR78A PR77B PR77A PR75B PR75A LFE2M100E/SE Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 RDQ81 RDQ81 RDQ81 RDQ81 RDQ72 RDQ72 C T C (LVDS)* T (LVDS)* C T RDQ81 RDQ81 RDQ81 RDQ81 C T C (LVDS)* T (LVDS)* RDQ81 RDQ81 RDQS81 T C (LVDS)* T (LVDS)* RDQ81 RDQ81 RDQ81 RDQ81 T C (LVDS)* T (LVDS)* C RDQ90 RDQ90 RDQ90 RDQ81 T C (LVDS)* T (LVDS)* C RDQ90 RDQ90 RDQ90 RDQ90 T C (LVDS)* T (LVDS)* C RDQ90 RDQS90 RDQ90 C (LVDS)* T (LVDS)* C RDQ90 RDQ90 RDQ90 RDQ90 C (LVDS)* T (LVDS)* C T RDQ99 RDQ99 RDQ99 RDQ99 RDQ90 RDQ90 C T C (LVDS)* T (LVDS)* C T Dual Function RDQ99 RDQ99 RDQ99 RDQ99 Differential C T C (LVDS)* T (LVDS)* 4-240 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number GNDIO AA28 AA29 AA30 AB30 VCCIO Y28 Y29 AA24 GNDIO Y25 Y31 Y30 Y24 VCCIO W25 Y33 Y34 W28 GNDIO V26 V28 V27 V25 VCCIO W24 W33 W34 GNDIO V24 U26 W29 W30 VCCIO U27 V29 V31 V32 V33 V34 GNDIO U24 U25 V30 Y32 VCCIO U28 U29 U33 GNDIO U34 Ball/Pad Function GNDIO3 PR66B PR66A PR65B PR65A VCCIO3 PR64B PR64A PR63B GNDIO3 PR63A PR62B PR62A PR61B VCCIO3 PR61A PR60B PR60A PR58B GNDIO3 PR58A PR57B PR57A PR56B VCCIO3 PR56A PR55B PR55A GNDIO3 PR54B PR54A PR53B PR53A VCCIO3 PR52B PR52A PR51B PR51A PR49B PR49A GNDIO2 PR48B PR48A PR47B PR47A VCCIO2 PR46B PR46A PR45B GNDIO2 PR45A Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 RDQ46 T RDQ46 RDQS46 RDQ46 C (LVDS)* T (LVDS)* C RDQ46 RDQ46 RDQ46 RDQ46 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ55 VREF1_3/RDQ55 PCLKC3_0/RDQ55 PCLKT3_0/RDQ55 PCLKC2_0/RDQ46 PCLKT2_0/RDQ46 C T C (LVDS)* T (LVDS)* C T RDQ55 RDQ55 RDQ55 RDQ55 C T C (LVDS)* T (LVDS)* RDQ55 RDQ55 RDQS55 T C (LVDS)* T (LVDS)* RLM3_SPLLT_FB_A/RDQ55 RLM3_SPLLC_IN_A/RDQ55 RLM3_SPLLT_IN_A/RDQ55 RDQ55 T C (LVDS)* T (LVDS)* C RDQ64 RDQ64 RDQ64 RLM3_SPLLC_FB_A/RDQ55 T C (LVDS)* T (LVDS)* C RDQ64 RDQ64 RDQ64 RDQ64 T C (LVDS)* T (LVDS)* C RDQ64 RDQS64 RDQ64 C (LVDS)* T (LVDS)* C RDQ64 RDQ64 RDQ64 RDQ64 C (LVDS)* T (LVDS)* C T Dual Function Differential Ball/Pad Function GNDIO3 PR74B PR74A PR73B PR73A VCCIO3 PR72B PR72A PR71B GNDIO3 PR71A PR70B PR70A PR69B VCCIO3 PR69A PR68B PR68A PR66B GNDIO3 PR66A PR65B PR65A PR64B VCCIO3 PR64A PR63B PR63A GNDIO3 PR62B PR62A PR61B PR61A VCCIO3 PR60B PR60A PR59B PR59A PR57B PR57A GNDIO2 PR56B PR56A PR55B PR55A VCCIO2 PR54B PR54A PR53B GNDIO2 PR53A LFE2M100E/SE Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 RDQ54 T RDQ54 RDQS54 RDQ54 C (LVDS)* T (LVDS)* C RDQ54 RDQ54 RDQ54 RDQ54 C (LVDS)* T (LVDS)* C T VREF2_3/RDQ63 VREF1_3/RDQ63 PCLKC3_0/RDQ63 PCLKT3_0/RDQ63 PCLKC2_0/RDQ54 PCLKT2_0/RDQ54 C T C (LVDS)* T (LVDS)* C T RDQ63 RDQ63 RDQ63 RDQ63 C T C (LVDS)* T (LVDS)* RDQ63 RDQ63 RDQS63 T C (LVDS)* T (LVDS)* RLM4_SPLLT_FB_A/RDQ63 RLM4_SPLLC_IN_A/RDQ63 RLM4_SPLLT_IN_A/RDQ63 RDQ63 T C (LVDS)* T (LVDS)* C RDQ72 RDQ72 RDQ72 RLM4_SPLLC_FB_A/RDQ63 T C (LVDS)* T (LVDS)* C RDQ72 RDQ72 RDQ72 RDQ72 T C (LVDS)* T (LVDS)* C RDQ72 RDQS72 RDQ72 C (LVDS)* T (LVDS)* C RDQ72 RDQ72 RDQ72 RDQ72 C (LVDS)* T (LVDS)* C T Dual Function Differential 4-241 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number T30 U30 T29 VCCIO T28 U31 U32 T33 T34 GNDIO R27 R28 R29 R30 VCCIO R33 R34 R32 GNDIO R31 P34 P33 R26 VCCIO T25 P28 P27 P30 P29 P31 P32 R25 T24 N34 N33 GNDIO M34 M33 R24 P24 N30 M29 VCCIO N28 N29 N24 GNDIO N25 Ball/Pad Function PR44B PR44A PR43B VCCIO2 PR43A PR42B PR42A PR40B PR40A GNDIO2 PR39B PR39A PR38B PR38A VCCIO2 PR37B PR37A PR36B GNDIO2 PR36A PR35B PR35A PR34B VCCIO2 PR34A PR33B PR33A NC NC NC NC NC NC NC NC GNDIO2 PR31B PR31A PR30B PR30A PR29B PR29A VCCIO2 PR28B PR28A PR27B GNDIO2 PR27A Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ28 T RDQ28 RDQS28 RDQ28 C (LVDS)* T (LVDS)* C RDQ28 RDQ28 RDQ28 RDQ28 C (LVDS)* T (LVDS)* C T RDQ28 RDQ28 C T RDQ37 RDQ37 RDQ37 T C (LVDS)* T (LVDS)* RDQ37 RDQ37 RDQ37 RDQ37 T C (LVDS)* T (LVDS)* C RDQ37 RDQS37 RDQ37 C (LVDS)* T (LVDS)* C RDQ37 RDQ37 RDQ37 RDQ37 C (LVDS)* T (LVDS)* C T RUM3_SPLLT_FB_A/RDQ46 RUM3_SPLLC_IN_A/RDQ46 RUM3_SPLLT_IN_A/RDQ46 RDQ37 RDQ37 T C (LVDS)* T (LVDS)* C T Dual Function RDQ46 RDQ46 RUM3_SPLLC_FB_A/RDQ46 Differential C (LVDS)* T (LVDS)* C Ball/Pad Function PR52B PR52A PR51B VCCIO2 PR51A PR50B PR50A PR48B PR48A GNDIO2 PR47B PR47A PR46B PR46A VCCIO2 PR45B PR45A PR44B GNDIO2 PR44A PR43B PR43A PR42B VCCIO2 PR42A PR41B PR41A PR40B GNDIO2 PR40A PR39B PR39A PR38B VCCIO2 PR38A PR37B PR37A GNDIO2 PR35B PR35A GNDIO2 PR34B PR34A PR33B PR33A VCCIO2 PR32B PR32A PR31B GNDIO2 PR31A LFE2M100E/SE Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDQ32 T RDQ32 RDQS32 RDQ32 C (LVDS)* T (LVDS)* C RDQ32 RDQ32 RDQ32 RDQ32 C (LVDS)* T (LVDS)* C T RDQ32 RDQ32 C T T C (LVDS)* T (LVDS)* T C (LVDS)* T (LVDS)* C RDQ45 RDQ45 RDQ45 T C (LVDS)* T (LVDS)* C RDQ45 RDQ45 RDQ45 RDQ45 T C (LVDS)* T (LVDS)* C RDQ45 RDQS45 RDQ45 C (LVDS)* T (LVDS)* C RDQ45 RDQ45 RDQ45 RDQ45 C (LVDS)* T (LVDS)* C T RUM3_SPLLT_FB_A/RDQ54 RUM3_SPLLC_IN_A/RDQ54 RUM3_SPLLT_IN_A/RDQ54 RDQ45 RDQ45 T C (LVDS)* T (LVDS)* C T Dual Function RDQ54 RDQ54 RUM3_SPLLC_FB_A/RDQ54 Differential C (LVDS)* T (LVDS)* C 4-242 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number M28 M27 L27 VCCIO M26 M32 M31 GNDIO L34 L33 L32 L31 VCCIO L28 L29 M30 L30 K34 K33 GNDIO K30 K29 J34 J33 VCCIO J32 J31 H33 GNDIO H34 J30 J29 VCCIO J27 J28 H31 GNDIO H32 VCCIO H30 B33 C33 B34 C32 B32 A33 C34 A32 B31 A31 Ball/Pad Function PR26B PR26A PR25B VCCIO2 PR25A PR24B PR24A GNDIO2 PR22B PR22A PR21B PR21A VCCIO2 PR20B PR20A PR19B PR19A PR18B PR18A GNDIO2 PR17B PR17A PR16B PR16A VCCIO2 PR15B PR15A PR14B GNDIO2 PR14A PR13B PR13A VCCIO2 PR11B PR11A PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 12 12 12 12 12 12 12 12 12 12 C C T C T VREF1_2 T RUM0_SPLLC_IN_A/RDQ15 RUM0_SPLLT_IN_A/RDQ15 VREF2_2 C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 T C (LVDS)* T (LVDS)* RDQ15 RDQS15 RDQ15 C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 RDQ15 C (LVDS)* T (LVDS)* C T RDQ15 RDQ15 C T C (LVDS)* T (LVDS)* C T C T C (LVDS)* T (LVDS)* RDQ28 RDQ28 RDQ28 T C (LVDS)* T (LVDS)* Dual Function RDQ28 RDQ28 RDQ28 Differential C (LVDS)* T (LVDS)* C Ball/Pad Function PR30B PR30A PR29B VCCIO2 PR29A PR28B PR28A GNDIO2 VCCIO2 PR22B PR22A PR21B PR21A VCCIO2 PR20B PR20A PR19B PR19A PR18B PR18A GNDIO2 PR17B PR17A PR16B PR16A VCCIO2 PR15B PR15A PR14B GNDIO2 PR14A PR13B PR13A VCCIO2 PR11B PR11A PR9B GNDIO2 PR9A VCCIO2 XRES URC_SQ_VCCRX0 URC_SQ_HDINP0 URC_SQ_VCCIB0 URC_SQ_HDINN0 URC_SQ_VCCTX0 URC_SQ_HDOUTP0 URC_SQ_VCCOB0 URC_SQ_HDOUTN0 URC_SQ_VCCTX1 URC_SQ_HDOUTN1 LFE2M100E/SE Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 12 12 12 12 12 12 12 12 12 12 C C T C T VREF1_2 T RUM0_SPLLC_IN_A/RDQ15 RUM0_SPLLT_IN_A/RDQ15 VREF2_2 C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 T C (LVDS)* T (LVDS)* RDQ15 RDQS15 RDQ15 C (LVDS)* T (LVDS)* C RDQ15 RDQ15 RDQ15 RDQ15 C (LVDS)* T (LVDS)* C T RDQ23 RDQ23 RDQ23 RDQ23 RDQ15 RDQ15 C T C (LVDS)* T (LVDS)* C T RDQ23 RDQ23 RDQ23 RDQ23 C T C (LVDS)* T (LVDS)* RDQ32 RDQ32 RDQ32 T C (LVDS)* T (LVDS)* Dual Function RDQ32 RDQ32 RDQ32 Differential C (LVDS)* T (LVDS)* C 4-243 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number D32 A30 B30 C31 D31 C30 E29 E30 D30 D29 C29 D27 C28 B29 A29 E28 A28 B28 A27 D26 A26 B27 C27 B26 C26 D28 E23 GNDIO F23 F24 G23 D23 VCCIO D22 C21 D21 GNDIO B21 A21 F22 E22 VCCIO GNDIO J22 G22 H22 K22 G21 Ball/Pad Function URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 PT82B GNDIO1 PT82A NC NC PT80B VCCIO1 PT80A PT79B PT79A GNDIO1 PT77B PT77A PT76B PT76A VCCIO1 GNDIO1 NC NC PT72B PT72A PT71B Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C C T C T C T T C T C T C T C C T C T C T T C T Dual Function Differential Ball/Pad Function URC_SQ_VCCOB1 URC_SQ_HDOUTP1 URC_SQ_VCCRX1 URC_SQ_HDINN1 URC_SQ_VCCIB1 URC_SQ_HDINP1 URC_SQ_VCCAUX33 URC_SQ_REFCLKN URC_SQ_REFCLKP URC_SQ_VCCP URC_SQ_HDINP2 URC_SQ_VCCIB2 URC_SQ_HDINN2 URC_SQ_VCCRX2 URC_SQ_HDOUTP2 URC_SQ_VCCOB2 URC_SQ_HDOUTN2 URC_SQ_VCCTX2 URC_SQ_HDOUTN3 URC_SQ_VCCOB3 URC_SQ_HDOUTP3 URC_SQ_VCCTX3 URC_SQ_HDINN3 URC_SQ_VCCIB3 URC_SQ_HDINP3 URC_SQ_VCCRX3 PT100B GNDIO1 PT100A PT99B PT99A PT98B VCCIO1 PT98A GNDIO1 VCCIO1 PT88B PT88A GNDIO1 PT86B PT86A PT85B PT85A VCCIO1 PT84B PT84A GNDIO1 PT81B PT81A PT80B LFE2M100E/SE Bank 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C C T C T C T C T T T C T C C T C T C C T C T C T T C T Dual Function Differential 4-244 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number VCCIO J21 H21 K21 D20 F20 C20 GNDIO E20 G20 VCCIO J20 A20 B20 GNDIO A19 B19 K20 H20 VCCIO L19 L20 E19 C18 GNDIO F19 D18 L18 K19 VCCIO A18 B18 G18 E18 F18 GNDIO G19 H18 K18 VCCIO J18 L17 G17 J17 H17 K17 B17 GNDIO A17 Ball/Pad Function VCCIO1 PT71A NC NC PT69B PT69A PT68B GNDIO1 PT68A PT67B VCCIO1 PT67A PT66B PT66A GNDIO1 PT63B PT63A PT62B PT62A VCCIO1 NC NC PT60B PT60A GNDIO1 PT59B PT59A NC NC VCCIO1 PT57B PT57A PT56B PT56A PT55B GNDIO0 PT55A PT54B PT54A VCCIO0 PT53B PT53A PT52B PT52A PT51B PT51A PT50B GNDIO0 PT50A Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 T T C T C C T C PCLKT0_0 VREF2_0 VREF1_0 T C T VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T C T C T T C T T C C T C T Dual Function Differential Ball/Pad Function VCCIO1 PT80A PT79B PT79A PT78B PT78A PT77B GNDIO1 PT77A PT76B VCCIO1 PT76A PT75B PT75A GNDIO1 PT72B PT72A PT71B PT71A VCCIO1 PT70B PT70A PT69B PT69A GNDIO1 PT68B PT68A PT67B PT67A VCCIO1 PT66B PT66A PT65B PT65A PT64B GNDIO0 PT64A PT63B PT63A VCCIO0 PT60B PT60A PT59B GNDIO0 PT59A PT58B VCCIO0 PT58A PT57B PT57A LFE2M100E/SE Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T T C T C C T C PCLKT0_0 VREF2_0 VREF1_0 T C T VREF2_1 VREF1_1 PCLKC1_0 PCLKT1_0 PCLKC0_0 C T C T C C T C T C T C T C T C T T C T T C T C T C T C Dual Function Differential 4-245 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number D17 VCCIO F17 B16 A16 E17 C17 K16 J15 GNDIO G16 H15 A15 B15 VCCIO L16 K15 F16 E16 E15 GNDIO G15 J14 L15 H14 VCCIO K14 F15 G14 C15 GNDIO D14 G13 J13 B14 VCCIO A14 F13 H13 D13 C14 GNDIO E13 D12 G12 E12 VCCIO F12 Ball/Pad Function PT49B VCCIO0 PT49A PT48B PT48A PT47B PT47A PT46B PT46A GNDIO0 PT45B PT45A PT44B PT44A VCCIO0 PT43B PT43A PT42B PT42A PT41B GNDIO0 PT41A NC NC NC VCCIO0 NC PT38B PT38A PT37B GNDIO0 PT37A PT36B PT36A PT35B VCCIO0 PT35A PT34B PT34A PT33B PT33A GNDIO0 PT32B PT32A PT31B PT31A VCCIO0 NC Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T T C T C T T C T C C T C T C T C T C C T C T C T C T T C T Dual Function Differential C Ball/Pad Function PT56B PT56A PT55B PT55A GNDIO0 VCCIO0 PT52B PT52A PT51B PT51A GNDIO0 PT50B PT50A PT49B PT49A VCCIO0 PT48B PT48A PT47B PT47A PT46B GNDIO0 PT46A PT45B PT45A PT44B VCCIO0 PT44A PT42B PT42A PT41B GNDIO0 PT41A PT40B VCCIO0 PT40A PT39B PT39A PT38B PT38A PT37B PT37A GNDIO0 PT32B PT32A PT31B PT31A VCCIO0 PT30B LFE2M100E/SE Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C T C T T C T C T T C T C T C T C T C T C C T C T C C T C T C T C T T C T Dual Function Differential C 4-246 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number D11 F11 E11 D7 C9 B9 C8 B8 A9 D9 A8 B7 A7 E7 A6 B6 C7 D8 C6 E6 E5 D5 D6 C5 D4 C4 B5 A5 D3 A4 B4 A3 C1 A2 B3 C3 B1 C2 B2 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB14 AB15 Ball/Pad Function NC NC NC ULC_SQ_VCCRX0 ULC_SQ_HDINP0 ULC_SQ_VCCIB0 ULC_SQ_HDINN0 ULC_SQ_VCCTX0 ULC_SQ_HDOUTP0 ULC_SQ_VCCOB0 ULC_SQ_HDOUTN0 ULC_SQ_VCCTX1 ULC_SQ_HDOUTN1 ULC_SQ_VCCOB1 ULC_SQ_HDOUTP1 ULC_SQ_VCCRX1 ULC_SQ_HDINN1 ULC_SQ_VCCIB1 ULC_SQ_HDINP1 ULC_SQ_VCCAUX33 ULC_SQ_REFCLKN ULC_SQ_REFCLKP ULC_SQ_VCCP ULC_SQ_HDINP2 ULC_SQ_VCCIB2 ULC_SQ_HDINN2 ULC_SQ_VCCRX2 ULC_SQ_HDOUTP2 ULC_SQ_VCCOB2 ULC_SQ_HDOUTN2 ULC_SQ_VCCTX2 ULC_SQ_HDOUTN3 ULC_SQ_VCCOB3 ULC_SQ_HDOUTP3 ULC_SQ_VCCTX3 ULC_SQ_HDINN3 ULC_SQ_VCCIB3 ULC_SQ_HDINP3 ULC_SQ_VCCRX3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Bank 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 T C T C C T C T C T T C T C C T C T Dual Function Differential Ball/Pad Function PT30A PT29B PT29A ULC_SQ_VCCRX0 ULC_SQ_HDINP0 ULC_SQ_VCCIB0 ULC_SQ_HDINN0 ULC_SQ_VCCTX0 ULC_SQ_HDOUTP0 ULC_SQ_VCCOB0 ULC_SQ_HDOUTN0 ULC_SQ_VCCTX1 ULC_SQ_HDOUTN1 ULC_SQ_VCCOB1 ULC_SQ_HDOUTP1 ULC_SQ_VCCRX1 ULC_SQ_HDINN1 ULC_SQ_VCCIB1 ULC_SQ_HDINP1 ULC_SQ_VCCAUX33 ULC_SQ_REFCLKN ULC_SQ_REFCLKP ULC_SQ_VCCP ULC_SQ_HDINP2 ULC_SQ_VCCIB2 ULC_SQ_HDINN2 ULC_SQ_VCCRX2 ULC_SQ_HDOUTP2 ULC_SQ_VCCOB2 ULC_SQ_HDOUTN2 ULC_SQ_VCCTX2 ULC_SQ_HDOUTN3 ULC_SQ_VCCOB3 ULC_SQ_HDOUTP3 ULC_SQ_VCCTX3 ULC_SQ_HDINN3 ULC_SQ_VCCIB3 ULC_SQ_HDINP3 ULC_SQ_VCCRX3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC LFE2M100E/SE Bank 0 0 0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 T C T C C T C T C T T C T C C T C T Dual Function Differential T C T 4-247 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AB20 AB21 N14 N15 N20 N21 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R13 R14 R21 R22 T14 T21 U14 U21 V14 V21 W14 W21 Y13 Y14 Y21 Y22 C12 C16 E14 H12 H16 M14 M15 C19 C23 E21 H19 H23 M20 M21 G32 K28 K32 N27 N32 Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 Bank 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 Dual Function Differential Ball/Pad Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 LFE2M100E/SE Bank 0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 Dual Function Differential 4-248 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number P23 R23 T27 T32 AA23 AB27 AB32 AE28 AE32 AH32 W27 W32 Y23 AC20 AC21 AG19 AG23 AK21 AM19 AM23 AC14 AC15 AG12 AG16 AK14 AM12 AM16 AA12 AB3 AB8 AE3 AE7 AH3 W3 W8 Y12 G3 K3 K7 N3 N8 P12 R12 T3 T8 AD28 AG32 AB12 AB13 AB22 AB23 Ball/Pad Function VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX Bank 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 Dual Function Differential Ball/Pad Function VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCAUX VCCAUX VCCAUX VCCAUX LFE2M100E/SE Bank 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 Dual Function Differential 4-249 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AC13 AC22 M13 M22 N12 N13 N22 N23 A1 A10 A13 A22 A25 A34 AB16 AB17 AB18 AB19 AB26 AB31 AB4 AB9 AC16 AC17 AC18 AC19 AD27 AE27 AE31 AE4 AE8 AF12 AF16 AF19 AF23 AG31 AH31 AH4 AJ14 AJ21 AK27 AK8 AL10 AL16 AL19 AL2 AL25 AL33 AP1 AP10 AP13 Ball/Pad Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential Ball/Pad Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFE2M100E/SE Bank Dual Function Differential 4-250 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AP22 AP25 AP34 D10 D16 D19 D2 D25 D33 E27 E8 F14 F21 G31 G4 J12 J16 J19 J23 K27 K31 K4 K8 M16 M17 M18 M19 N16 N17 N18 N19 N26 N31 N4 N9 R16 R17 R18 R19 T12 T13 T15 T16 T17 T18 T19 T20 T22 T23 T26 T31 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFE2M100E/SE Bank Dual Function Differential 4-251 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number T4 T9 U12 U13 U15 U16 U17 U18 U19 U20 U22 U23 V12 V13 V15 V16 V17 V18 V19 V20 V22 V23 W12 W13 W15 W16 W17 W18 W19 W20 W22 W23 W26 W31 W4 W9 Y16 Y17 Y18 Y19 A11 A12 A23 A24 AA11 AB11 AC26 AC30 AD11 AD12 AD13 Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential Ball/Pad Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC LFE2M100E/SE Bank Dual Function Differential 4-252 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AD14 AD15 AD19 AD21 AD22 AD23 AE10 AE11 AE12 AE13 AE19 AE21 AE22 AE23 AF11 AF21 AF22 AF24 AF8 AF9 AG10 AG11 AG24 AG25 AG26 AG3 AG7 AG8 AG9 AH10 AH11 AH13 AH24 AH25 AH26 AH27 AH5 AH6 AH7 AH8 AH9 AJ10 AJ11 AJ13 AJ24 AJ25 AJ26 AJ27 AJ3 AJ4 AJ5 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC LFE2M100E/SE Bank Dual Function Differential 4-253 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number AJ6 AJ7 AJ8 AJ9 AK10 AK11 AK12 AK24 AK25 AK26 AK4 AK9 AL11 AL12 AL34 AM10 AM11 AM13 AM25 AN10 AN11 AN12 AN13 AN24 AN25 AP11 AP12 AP24 B10 B11 B12 B13 B22 B23 B24 B25 C10 C11 C13 C22 C24 C25 D1 D15 D24 D34 E10 E24 E25 E26 E3 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC LFE2M100E/SE Bank Dual Function Differential 4-254 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number E31 E32 E33 E34 E4 E9 F10 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F5 F6 F7 F8 F9 G10 G11 G24 G25 G26 G27 G28 G29 G30 G33 G34 G7 G8 G9 H10 H11 H24 H25 H26 H27 H28 H29 H8 H9 J10 J11 J24 J25 J26 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Bank Dual Function Differential Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC LFE2M100E/SE Bank Dual Function Differential 4-255 Lattice Semiconductor Pinout Information LatticeECP2/M Family Data Sheet LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA LFE2M70E/SE Ball Number J9 K10 K11 K12 K13 K23 K24 K25 K26 L11 L12 L13 L14 L21 L22 L23 L24 L25 L26 M11 M24 M25 M6 M8 N10 N11 P10 P25 P26 R9 T11 U11 W11 Y10 Y11 R15 R20 Y15 Y20 Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCPLL VCCPLL VCCPLL VCCPLL Bank Dual Function Differential Ball/Pad Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCPLL VCCPLL VCCPLL VCCPLL LFE2M100E/SE Bank Dual Function Differential * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70, and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. 4-256 LatticeECP2/M Family Data Sheet Ordering Information August 2007 Data Sheet DS1006 LatticeECP2 Part Number Description LFE2 - XX XE - X XXXXXX X Device Family ECP2 (LatticeECP2 FPGA) Logic Capacity 6 = 6K LUTs 12 = 12K LUTs 20 = 20K LUTs 35 = 35K LUTs 50 = 50K LUTs 70 = 70K LUTs Encryption S = Security Series (Encryption Feature) Blank = Standard Series (No Encryption) Supply Voltage E = 1.2V Grade C = Commercial I = Industrial Package T144 = 144-pin TQFP Q208 = 208-pin PQFP F256 = 256-ball fpBGA F484 = 484-ball fpBGA F672 = 672-ball fpBGA F900 = 900-ball fpBGA TN144 = 144-pin Lead-Free TQFP QN208 = 208-pin Lead-Free PQFP FN256 = 256-ball Lead-Free fpBGA FN484 = 484-ball Lead-Free fpBGA FN672 = 672-ball Lead-Free fpBGA FN900 = 900-ball Lead-Free fpBGA Speed 5 = Slowest 6 7 = Fastest Ordering Information Note: LatticeECP2 devices are dual marked. For example, the commercial speed grade LFE2-50E-7F672C is also marked with industrial grade -6I (LFE2-50E-6F672I). The commercial grade is one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings. The markings appear as follows: LFE2-50E 7F672C-6I Datecode LFE2-50SE 7F672C-6I Datecode (c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1006 Order Info_01.5 Lattice Semiconductor Ordering Information LatticeECP2/M Family Data Sheet LatticeECP2 Standard Series Devices, Conventional Packaging Commercial Part Number LFE2-6E-5T144C LFE2-6E-6T144C LFE2-6E-7T144C LFE2-6E-5F256C LFE2-6E-6F256C LFE2-6E-7F256C I/Os 90 90 90 190 190 190 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package TQFP TQFP TQFP fpBGA fpBGA fpBGA Pins 144 144 144 256 256 256 Temp. COM COM COM COM COM COM LUTs (K) 6 6 6 6 6 6 Part Number LFE2-12E-5T144C LFE2-12E-6T144C LFE2-12E-7T144C LFE2-12E-5Q208C LFE2-12E-6Q208C LFE2-12E-7Q208C LFE2-12E-5F256C LFE2-12E-6F256C LFE2-12E-7F256C LFE2-12E-5F484C LFE2-12E-6F484C LFE2-12E-7F484C I/Os 93 93 93 131 131 131 193 193 193 297 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package TQFP TQFP TQFP PQFP PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 144 144 144 208 208 208 256 256 256 484 484 484 Temp. COM COM COM COM COM COM COM COM COM COM COM COM LUTs (K) 12 12 12 12 12 12 12 12 12 12 12 12 Part Number LFE2-20E-5Q208C LFE2-20E-6Q208C LFE2-20E-7Q208C LFE2-20E-5F256C LFE2-20E-6F256C LFE2-20E-7F256C LFE2-20E-5F484C LFE2-20E-6F484C LFE2-20E-7F484C LFE2-20E-5F672C LFE2-20E-6F672C LFE2-20E-7F672C I/Os 131 131 131 193 193 193 331 331 331 402 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package PQFP PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 208 208 208 256 256 256 484 484 484 672 672 672 Temp. COM COM COM COM COM COM COM COM COM COM COM COM LUTs (K) 20 20 20 20 20 20 20 20 20 20 20 20 5-2 Lattice Semiconductor Part Number LFE2-35E-5F484C LFE2-35E-6F484C LFE2-35E-7F484C LFE2-35E-5F672C LFE2-35E-6F672C LFE2-35E-7F672C I/Os 331 331 331 450 450 450 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 672 672 672 Temp. COM COM COM COM COM COM LUTs (K) 35 35 35 35 35 35 Part Number LFE2-50E-5F484C LFE2-50E-6F484C LFE2-50E-7F484C LFE2-50E-5F672C LFE2-50E-6F672C LFE2-50E-7F672C I/Os 339 339 339 500 500 500 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 672 672 672 Temp. COM COM COM COM COM COM LUTs (K) 50 50 50 50 50 50 Part Number LFE2-70E-5F672C LFE2-70E-6F672C LFE2-70E-7F672C LFE2-70E-5F900C LFE2-70E-6F900C LFE2-70E-7F900C I/Os 500 500 500 583 583 583 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 672 672 672 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 70 70 70 70 70 70 Industrial Part Number LFE2-6E-5T144I LFE2-6E-6T144I LFE2-6E-5F256I LFE2-6E-6F256I I/Os 90 90 190 190 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package TQFP TQFP fpBGA fpBGA Pins 144 144 256 256 Temp. IND IND IND IND LUTs (K) 6 6 6 6 Part Number LFE2-12E-5T144I LFE2-12E-6T144I LFE2-12E-5Q208I LFE2-12E-6Q208I LFE2-12E-5F256I LFE2-12E-6F256I LFE2-12E-5F484I LFE2-12E-6F484I I/Os 93 93 131 131 193 193 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Package TQFP TQFP PQFP PQFP fpBGA fpBGA fpBGA fpBGA Pins 144 144 208 208 256 256 484 484 Temp. IND IND IND IND IND IND IND IND LUTs (K) 12 12 12 12 12 12 12 12 5-3 Lattice Semiconductor Part Number LFE2-20E-5Q208I LFE2-20E-6Q208I LFE2-20E-5F256I LFE2-20E-6F256I LFE2-20E-5F484I LFE2-20E-6F484I LFE2-20E-5F672I LFE2-20E-6F672I I/Os 131 131 193 193 331 331 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Ordering Information LatticeECP2/M Family Data Sheet Package PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 208 208 256 256 484 484 672 672 Temp. IND IND IND IND IND IND IND IND LUTs (K) 20 20 20 20 20 20 20 20 Part Number LFE2-35E-5F484I LFE2-35E-6F484I LFE2-35E-5F672I LFE2-35E-6F672I I/Os 331 331 450 450 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 672 672 Temp. IND IND IND IND LUTs (K) 35 35 35 35 Part Number LFE2-50E-5F484I LFE2-50E-6F484I LFE2-50E-5F672I LFE2-50E-6F672I I/Os 339 339 500 500 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 672 672 Temp. IND IND IND IND LUTs (K) 50 50 50 50 Part Number LFE2-70E-5F672I LFE2-70E-6F672I LFE2-70E-5F900I LFE2-70E-6F900I I/Os 500 500 583 583 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 672 672 900 900 Temp. IND IND IND IND LUTs (K) 70 70 70 70 5-4 Lattice Semiconductor Ordering Information LatticeECP2/M Family Data Sheet LatticeECP2 Standard Series Devices, Lead-Free Packaging Commercial Part Number LFE2-6E-5TN144C LFE2-6E-6TN144C LFE2-6E-7TN144C LFE2-6E-5FN256C LFE2-6E-6FN256C LFE2-6E-7FN256C I/Os 90 90 90 190 190 190 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 144 256 256 256 Temp. COM COM COM COM COM COM LUTs (K) 6 6 6 6 6 6 Part Number LFE2-12E-5TN144C LFE2-12E-6TN144C LFE2-12E-7TN144C LFE2-12E-5QN208C LFE2-12E-6QN208C LFE2-12E-7QN208C LFE2-12E-5FN256C LFE2-12E-6FN256C LFE2-12E-7FN256C LFE2-12E-5FN484C LFE2-12E-6FN484C LFE2-12E-7FN484C I/Os 93 93 93 131 131 131 193 193 193 297 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 144 208 208 208 256 256 256 484 484 484 Temp. COM COM COM COM COM COM COM COM COM COM COM COM LUTs (K) 12 12 12 12 12 12 12 12 12 12 12 12 Part Number LFE2-20E-5QN208C LFE2-20E-6QN208C LFE2-20E-7QN208C LFE2-20E-5FN256C LFE2-20E-6FN256C LFE2-20E-7FN256C LFE2-20E-5FN484C LFE2-20E-6FN484C LFE2-20E-7FN484C LFE2-20E-5FN672C LFE2-20E-6FN672C LFE2-20E-7FN672C I/Os 131 131 131 193 193 193 331 331 331 402 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 208 208 208 256 256 256 484 484 484 672 672 672 Temp. COM COM COM COM COM COM COM COM COM COM COM COM LUTs (K) 20 20 20 20 20 20 20 20 20 20 20 20 5-5 Lattice Semiconductor Part Number LFE2-35E-5FN484C LFE2-35E-6FN484C LFE2-35E-7FN484C LFE2-35E-5FN672C LFE2-35E-6FN672C LFE2-35E-7FN672C I/Os 331 331 331 450 450 450 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 484 672 672 672 Temp. COM COM COM COM COM COM LUTs (K) 35 35 35 35 35 35 Part Number LFE2-50E-5FN484C LFE2-50E-6FN484C LFE2-50E-7FN484C LFE2-50E-5FN672C LFE2-50E-6FN672C LFE2-50E-7FN672C I/Os 339 339 339 500 500 500 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 484 672 672 672 Temp. COM COM COM COM COM COM LUTs (K) 50 50 50 50 50 50 Part Number LFE2-70E-5FN672C LFE2-70E-6FN672C LFE2-70E-7FN672C LFE2-70E-5FN900C LFE2-70E-6FN900C LFE2-70E-7FN900C I/Os 500 500 500 583 583 583 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 672 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 70 70 70 70 70 70 Industrial Part Number LFE2-6E-5TN144I LFE2-6E-6TN144I LFE2-6E-5FN256I LFE2-6E-6FN256I I/Os 90 90 190 190 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free TQFP Lead-Free TQFP Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 256 256 Temp. IND IND IND IND LUTs (K) 6 6 6 6 Part Number LFE2-12E-5TN144I LFE2-12E-6TN144I LFE2-12E-5QN208I LFE2-12E-6QN208I LFE2-12E-5FN256I LFE2-12E-6FN256I LFE2-12E-5FN484I LFE2-12E-6FN484I I/Os 93 93 131 131 193 193 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Package Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 208 208 256 256 484 484 Temp. IND IND IND IND IND IND IND IND LUTs (K) 12 12 12 12 12 12 12 12 5-6 Lattice Semiconductor Part Number LFE2-20E-5QN208I LFE2-20E-6QN208I LFE2-20E-5FN256I LFE2-20E-6FN256I LFE2-20E-5FN484I LFE2-20E-6FN484I LFE2-20E-5FN672I LFE2-20E-6FN672I I/Os 131 131 193 193 331 331 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 208 208 256 256 484 484 672 672 Temp. IND IND IND IND IND IND IND IND LUTs (K) 20 20 20 20 20 20 20 20 Part Number LFE2-35E-5FN484I LFE2-35E-6FN484I LFE2-35E-5FN672I LFE2-35E-6FN672I I/Os 331 331 450 450 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 672 672 Temp. IND IND IND IND LUTs (K) 35 35 35 35 Part Number LFE2-50E-5FN484I LFE2-50E-6FN484I LFE2-50E-5FN672I LFE2-50E-6FN672I I/Os 339 339 500 500 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 672 672 Temp. IND IND IND IND LUTs (K) 50 50 50 50 Part Number LFE2-70E-5FN672I LFE2-70E-6FN672I LFE2-70E-5FN900I LFE2-70E-6FN900I I/Os 500 500 583 583 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 900 900 Temp. IND IND IND IND LUTs (K) 70 70 70 70 5-7 Lattice Semiconductor Ordering Information LatticeECP2/M Family Data Sheet LatticeECP2 S-Series Devices, Conventional Packaging Commercial Part Number LFE2-6SE-5T144C LFE2-6SE-6T144C LFE2-6SE-7T144C LFE2-6SE-5F256C LFE2-6SE-6F256C LFE2-6SE-7F256C I/Os 90 90 90 190 190 190 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package TQFP TQFP TQFP fpBGA fpBGA fpBGA Pins 144 144 144 256 256 256 Temp. Com Com Com Com Com Com LUTs (K) 6 6 6 6 6 6 Part Number LFE2-12SE-5T144C LFE2-12SE-6T144C LFE2-12SE-7T144C LFE2-12SE-5Q208C LFE2-12SE-6Q208C LFE2-12SE-7Q208C LFE2-12SE-5F256C LFE2-12SE-6F256C LFE2-12SE-7F256C LFE2-12SE-5F484C LFE2-12SE-6F484C LFE2-12SE-7F484C I/Os 93 93 93 131 131 131 193 193 193 297 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package TQFP TQFP TQFP PQFP PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 144 144 144 208 208 208 256 256 256 484 484 484 Temp. Com Com Com Com Com Com Com Com Com Com Com Com LUTs (K) 12 12 12 12 12 12 12 12 12 12 12 12 Part Number LFE2-20SE-5Q208C LFE2-20SE-6Q208C LFE2-20SE-7Q208C LFE2-20SE-5F256C LFE2-20SE-6F256C LFE2-20SE-7F256C LFE2-20SE-5F484C LFE2-20SE-6F484C LFE2-20SE-7F484C LFE2-20SE-5F672C LFE2-20SE-6F672C LFE2-20SE-7F672C I/Os 131 131 131 193 193 193 331 331 331 402 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package PQFP PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 208 208 208 256 256 256 484 484 484 672 672 672 Temp. Com Com Com Com Com Com Com Com Com Com Com Com LUTs (K) 20 20 20 20 20 20 20 20 20 20 20 20 5-8 Lattice Semiconductor Part Number LFE2-35SE-5F484C LFE2-35SE-6F484C LFE2-35SE-7F484C LFE2-35SE-5F672C LFE2-35SE-6F672C LFE2-35SE-7F672C I/Os 331 331 331 450 450 450 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 672 672 672 Temp. Com Com Com Com Com Com LUTs (K) 35 35 35 35 35 35 Part Number LFE2-50SE-5F484C LFE2-50SE-6F484C LFE2-50SE-7F484C LFE2-50SE-5F672C LFE2-50SE-6F672C LFE2-50SE-7F672C I/Os 339 339 339 500 500 500 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 672 672 672 Temp. Com Com Com Com Com Com LUTs (K) 50 50 50 50 50 50 Part Number LFE2-70SE-5F672C LFE2-70SE-6F672C LFE2-70SE-7F672C LFE2-70SE-5F900C LFE2-70SE-6F900C LFE2-70SE-7F900C I/Os 500 500 500 583 583 583 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 672 672 672 900 900 900 Temp. Com Com Com Com Com Com LUTs (K) 70 70 70 70 70 70 Industrial Part Number LFE2-6SE-5T144I LFE2-6SE-6T144I LFE2-6SE-5F256I LFE2-6SE-6F256I I/Os 90 90 190 190 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package TQFP TQFP fpBGA fpBGA Pins 144 144 256 256 Temp. Ind Ind Ind Ind LUTs (K) 6 6 6 6 Part Number LFE2-12SE-5T144I LFE2-12SE-6T144I LFE2-12SE-5Q208I LFE2-12SE-6Q208I LFE2-12SE-5F256I LFE2-12SE-6F256I LFE2-12SE-5F484I LFE2-12SE-6F484I I/Os 93 93 131 131 193 193 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Package TQFP TQFP PQFP PQFP fpBGA fpBGA fpBGA fpBGA Pins 144 144 208 208 256 256 484 484 Temp. Ind Ind Ind Ind Ind Ind Ind Ind LUTs (K) 12 12 12 12 12 12 12 12 5-9 Lattice Semiconductor Part Number LFE2-20SE-5Q208I LFE2-20SE-6Q208I LFE2-20SE-5F256I LFE2-20SE-6F256I LFE2-20SE-5F484I LFE2-20SE-6F484I LFE2-20SE-5F672I LFE2-20SE-6F672I I/Os 131 131 193 193 331 331 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Ordering Information LatticeECP2/M Family Data Sheet Package PQFP PQFP fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 208 208 256 256 484 484 672 672 Temp. Ind Ind Ind Ind Ind Ind Ind Ind LUTs (K) 20 20 20 20 20 20 20 20 Part Number LFE2-35SE-5F484I LFE2-35SE-6F484I LFE2-35SE-5F672I LFE2-35SE-6F672I I/Os 331 331 450 450 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 672 672 Temp. Ind Ind Ind Ind LUTs (K) 35 35 35 35 Part Number LFE2-50SE-5F484I LFE2-50SE-6F484I LFE2-50SE-5F672I LFE2-50SE-6F672I I/Os 339 339 500 500 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 672 672 Temp. Ind Ind Ind Ind LUTs (K) 50 50 50 50 Part Number LFE2-70SE-5F672I LFE2-70SE-6F672I LFE2-70SE-5F900I LFE2-70SE-6F900I I/Os 500 500 583 583 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 672 672 900 900 Temp. Ind Ind Ind Ind LUTs (K) 70 70 70 70 5-10 Lattice Semiconductor LatticeECP2 S-Series Devices, Lead-Free Packaging Commercial Part Number LFE2-6SE-5TN144C LFE2-6SE-6TN144C LFE2-6SE-7TN144C LFE2-6SE-5FN256C LFE2-6SE-6FN256C LFE2-6SE-7FN256C I/Os 90 90 90 190 190 190 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 144 256 256 256 Temp. Com Com Com Com Com Com LUTs (K) 6 6 6 6 6 6 Part Number LFE2-12SE-5TN144C LFE2-12SE-6TN144C LFE2-12SE-7TN144C LFE2-12SE-5QN208C LFE2-12SE-6QN208C LFE2-12SE-7QN208C LFE2-12SE-5FN256C LFE2-12SE-6FN256C LFE2-12SE-7FN256C LFE2-12SE-5FN484C LFE2-12SE-6FN484C LFE2-12SE-7FN484C I/Os 93 93 93 131 131 131 193 193 193 297 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 144 208 208 208 256 256 256 484 484 484 Temp. Com Com Com Com Com Com Com Com Com Com Com Com LUTs (K) 12 12 12 12 12 12 12 12 12 12 12 12 Part Number LFE2-20SE-5QN208C LFE2-20SE-6QN208C LFE2-20SE-7QN208C LFE2-20SE-5FN256C LFE2-20SE-6FN256C LFE2-20SE-7FN256C LFE2-20SE-5FN484C LFE2-20SE-6FN484C LFE2-20SE-7FN484C LFE2-20SE-5FN672C LFE2-20SE-6FN672C LFE2-20SE-7FN672C I/Os 131 131 131 193 193 193 331 331 331 402 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free PQFP Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 208 208 208 256 256 256 484 484 484 672 672 672 Temp. Com Com Com Com Com Com Com Com Com Com Com Com LUTs (K) 20 20 20 20 20 20 20 20 20 20 20 20 5-11 Lattice Semiconductor Part Number LFE2-35SE-5FN484C LFE2-35SE-6FN484C LFE2-35SE-7FN484C LFE2-35SE-5FN672C LFE2-35SE-6FN672C LFE2-35SE-7FN672C I/Os 331 331 331 450 450 450 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 484 672 672 672 Temp. Com Com Com Com Com Com LUTs (K) 35 35 35 35 35 35 Part Number LFE2-50SE-5FN484C LFE2-50SE-6FN484C LFE2-50SE-7FN484C LFE2-50SE-5FN672C LFE2-50SE-6FN672C LFE2-50SE-7FN672C I/Os 339 339 339 500 500 500 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 484 672 672 672 Temp. Com Com Com Com Com Com LUTs (K) 50 50 50 50 50 50 Part Number LFE2-70SE-5FN672C LFE2-70SE-6FN672C LFE2-70SE-7FN672C LFE2-70SE-5FN900C LFE2-70SE-6FN900C LFE2-70SE-7FN900C I/Os 500 500 500 583 583 583 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 672 900 900 900 Temp. Com Com Com Com Com Com LUTs (K) 70 70 70 70 70 70 Industrial Part Number LFE2-6SE-5TN144I LFE2-6SE-6TN144I LFE2-6SE-5FN256I LFE2-6SE-6FN256I I/Os 90 90 190 190 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free TQFP Lead-Free TQFP Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 256 256 Temp. Ind Ind Ind Ind LUTs (K) 6 6 6 6 Part Number LFE2-12SE-5TN144I LFE2-12SE-6TN144I LFE2-12SE-5QN208I LFE2-12SE-6QN208I LFE2-12SE-5FN256I LFE2-12SE-6FN256I LFE2-12SE-5FN484I LFE2-12SE-6FN484I I/Os 93 93 131 131 193 193 297 297 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Package Lead-Free TQFP Lead-Free TQFP Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 144 144 208 208 256 256 484 484 Temp. Ind Ind Ind Ind Ind Ind Ind Ind LUTs (K) 12 12 12 12 12 12 12 12 5-12 Lattice Semiconductor Part Number LFE2-20SE-5QN208I LFE2-20SE-6QN208I LFE2-20SE-5FN256I LFE2-20SE-6FN256I LFE2-20SE-5FN484I LFE2-20SE-6FN484I LFE2-20SE-5FN672I LFE2-20SE-6FN672I I/Os 131 131 193 193 331 331 402 402 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 -5 -6 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free PQFP Lead-Free PQFP Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 208 208 256 256 484 484 672 672 Temp. Ind Ind Ind Ind Ind Ind Ind Ind LUTs (K) 20 20 20 20 20 20 20 20 Part Number LFE2-35SE-5FN484I LFE2-35SE-6FN484I LFE2-35SE-5FN672I LFE2-35SE-6FN672I I/Os 331 331 450 450 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 672 672 Temp. Ind Ind Ind Ind LUTs (K) 35 35 35 35 Part Number LFE2-50SE-5FN484I LFE2-50SE-6FN484I LFE2-50SE-5FN672I LFE2-50SE-6FN672I I/Os 339 339 500 500 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 672 672 Temp. Ind Ind Ind Ind LUTs (K) 50 50 50 50 Part Number LFE2-70SE-5FN672I LFE2-70SE-6FN672I LFE2-70SE-5FN900I LFE2-70SE-6FN900I I/Os 500 500 583 583 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 900 900 Temp. Ind Ind Ind Ind LUTs (K) 70 70 70 70 5-13 Lattice Semiconductor Ordering Information LatticeECP2/M Family Data Sheet LatticeECP2M Part Number Description LFE2M XXX XE - X XXXXXX X Device Family ECP2M (LatticeECP2 FPGA + SERDES) Logic Capacity 20 = 20K LUTs 35 = 35K LUTs 50 = 50K LUTs 70 = 70K LUTs 100 = 100K LUTs Encryption S = Security Series (Encryption Feature) Blank = Standard Series (No Encryption) Supply Voltage E = 1.2V Grade C = Commercial I = Industrial Package F256 = 256-ball fpBGA F484 = 484-ball fpBGA F672 = 672-ball fpBGA F900 = 900-ball fpBGA F1152 = 1152-ball fpBGA F1156 = 1156-ball fpBGA FN256 = 256-ball Lead-free fpBGA FN484 = 484-ball Lead-free fpBGA FN672 = 672-ball Lead-free fpBGA FN900 = 900-ball Lead-free fpBGA FN1152 = 1152-ball Lead-free fpBGA FN1156 = 1156-ball Lead-free fpBGA Speed 5 = Slowest 6 7 = Fastest Ordering Information Note: LatticeECP2M devices are dual marked. For example, the commercial speed grade LFE2M50E-7F672C is also marked with industrial grade -6I (LFE2M50E-6F672I). The commercial grade is one speed grade faster than the associated dual mark industrial grade. The slowest commercial grade does not have industrial markings. The markings appear as follows: LFE2M35E 7F672C-6I Datecode LFE2M35SE 7F672C-6I Datecode Contact Your Local Lattice Sales Representative for Product Availability. 5-14 Lattice Semiconductor Ordering Information LatticeECP2/M Family Data Sheet LatticeECP2M Standard Series Devices, Conventional Packaging Commercial Part Number LFE2M20E-5F484C LFE2M20E-6F484C LFE2M20E-7F484C LFE2M20E-5F256C LFE2M20E-6F256C LFE2M20E-7F256C I/Os 304 304 304 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 256 256 256 Temp. COM COM COM COM COM COM LUTs (K) 20 20 20 20 20 20 Part Number LFE2M35E-5F672C LFE2M35E-6F672C LFE2M35E-7F672C LFE2M35E-5F484C LFE2M35E-6F484C LFE2M35E-7F484C LFE2M35E-5F256C LFE2M35E-6F256C LFE2M35E-7F256C I/Os 410 410 410 303 303 303 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 672 672 672 484 484 484 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs (K) 35 35 35 35 35 35 35 35 35 Part Number LFE2M50E-5F900C LFE2M50E-6F900C LFE2M50E-7F900C LFE2M50E-5F672C LFE2M50E-6F672C LFE2M50E-7F672C LFE2M50E-5F484C LFE2M50E-6F484C LFE2M50E-7F484C I/Os 410 410 410 372 372 372 270 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 900 900 900 672 672 672 484 484 484 Temp. COM COM COM COM COM COM COM COM COM LUTs (K) 50 50 50 50 50 50 50 50 50 Part Number LFE2M70E-5F1152C LFE2M70E-6F1152C LFE2M70E-7F1152C LFE2M70E-5F900C LFE2M70E-6F900C LFE2M70E-7F900C I/Os 436 436 436 416 416 416 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 1152 1152 1152 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 70 70 70 70 70 70 5-15 Lattice Semiconductor Part Number LFE2M100E-5F1152C LFE2M100E-6F1152C LFE2M100E-7F1152C LFE2M100E-5F900C LFE2M100E-6F900C LFE2M100E-7F900C I/Os 520 520 520 416 416 416 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 1152 1152 1152 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 100 100 100 100 100 100 5-16 Lattice Semiconductor Industrial Part Number LFE2M20E-5F484I LFE2M20E-6F484I LFE2M20E-5F256I LFE2M20E-6F256I I/Os 304 304 140 140 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Ordering Information LatticeECP2/M Family Data Sheet Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 256 256 Temp. IND IND IND IND LUTs (K) 20 20 20 20 Part Number LFE2M35E-5F672I LFE2M35E-6F672I LFE2M35E-5F484I LFE2M35E-6F484I LFE2M35E-5F256I LFE2M35E-6F256I I/Os 410 410 303 303 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 672 672 484 484 256 256 Temp. IND IND IND IND IND IND LUTs (K) 35 35 35 35 35 35 Part Number LFE2M50E-5F900I LFE2M50E-6F900I LFE2M50E-5F672I LFE2M50E-6F672I LFE2M50E-5F484I LFE2M50E-6F484I I/Os 410 410 372 372 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 900 900 672 672 484 484 Temp. IND IND IND IND IND IND LUTs (K) 50 50 50 50 50 50 Part Number LFE2M70E-5F1152I LFE2M70E-6F1152I LFE2M70E-5F900I LFE2M70E-6F900I I/Os 436 436 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 1152 1152 900 900 Temp. IND IND IND IND LUTs (K) 70 70 70 70 Part Number LFE2M100E-5F1152I LFE2M100E-6F1152I LFE2M100E-5F900I LFE2M100E-6F900I I/Os 520 520 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 1152 1152 900 900 Temp. IND IND IND IND LUTs (K) 100 100 100 100 5-17 Lattice Semiconductor Ordering Information LatticeECP2/M Family Data Sheet LatticeECP2M Standard Series Devices, Lead-Free Packaging Commercial Part Number LFE2M20E-5FN484C LFE2M20E-6FN484C LFE2M20E-7FN484C LFE2M20E-5FN256C LFE2M20E-6FN256C LFE2M20E-7FN256C I/Os 304 304 304 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 484 256 256 256 Temp. COM COM COM COM COM COM LUTs (K) 20 20 20 20 20 20 Part Number LFE2M35E-5FN672C LFE2M35E-6FN672C LFE2M35E-7FN672C LFE2M35E-5FN484C LFE2M35E-6FN484C LFE2M35E-7FN484C LFE2M35E-5FN256C LFE2M35E-6FN256C LFE2M35E-7FN256C I/Os 410 410 410 303 303 303 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 672 484 484 484 256 256 256 Temp. COM COM COM COM COM COM COM COM COM LUTs (K) 35 35 35 35 35 35 35 35 35 Part Number LFE2M50E-5FN900C LFE2M50E-6FN900C LFE2M50E-7FN900C LFE2M50E-5FN672C LFE2M50E-6FN672C LFE2M50E-7FN672C LFE2M50E-5FN484C LFE2M50E-6FN484C LFE2M50E-7FN484C I/Os 410 410 410 372 372 372 270 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 900 900 900 672 672 672 484 484 484 Temp. COM COM COM COM COM COM COM COM COM LUTs (K) 50 50 50 50 50 50 50 50 50 Part Number LFE2M70E-5FN1152C LFE2M70E-6FN1152C LFE2M70E-7FN1152C LFE2M70E-5FN900C LFE2M70E-6FN900C LFE2M70E-7FN900C I/Os 436 436 436 416 416 416 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 1152 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 70 70 70 70 70 70 5-18 Lattice Semiconductor Part Number LFE2M100E-5FN1152C LFE2M100E-6FN1152C LFE2M100E-7FN1152C LFE2M100E-5FN900C LFE2M100E-6FN900C LFE2M100E-7FN900C I/Os 520 520 520 416 416 416 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 1152 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 100 100 100 100 100 100 Industrial Part Number LFE2M20E-5FN484I LFE2M20E-6FN484I LFE2M20E-5FN256I LFE2M20E-6FN256I I/Os 304 304 140 140 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 256 256 Temp. IND IND IND IND LUTs (K) 20 20 20 20 Part Number LFE2M35E-5FN672I LFE2M35E-6FN672I LFE2M35E-5FN484I LFE2M35E-6FN484I LFE2M35E-5FN256I LFE2M35E-6FN256I I/Os 410 410 303 303 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 484 484 256 256 Temp. IND IND IND IND IND IND LUTs (K) 35 35 35 35 35 35 Part Number LFE2M50E-5FN900I LFE2M50E-6FN900I LFE2M50E-5FN672I LFE2M50E-6FN672I LFE2M50E-5FN484I LFE2M50E-6FN484I I/Os 410 410 372 372 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 900 900 672 672 484 484 Temp. Ind Ind Ind Ind Ind Ind LUTs (K) 50 50 50 50 50 50 Part Number LFE2M70E-5FN1152I LFE2M70E-6FN1152I LFE2M70E-5FN900I LFE2M70E-6FN900I I/Os 436 436 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 900 900 Temp. Ind Ind Ind Ind LUTs (K) 70 70 70 70 5-19 Lattice Semiconductor Ordering Information LatticeECP2/M Family Data Sheet Part Number LFE2M100E-5FN1152I LFE2M100E-6FN1152I LFE2M100E-5FN900I LFE2M100E-6FN900I I/Os 520 520 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 900 900 Temp. Ind Ind Ind Ind LUTs (K) 100 100 100 100 LatticeECP2M S-Series Devices, Conventional Packaging Commercial Part Number LFE2M20SE-5F484C LFE2M20SE-6F484C LFE2M20SE-7F484C LFE2M20SE-5F256C LFE2M20SE-6F256C LFE2M20SE-7F256C I/Os 304 304 304 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 484 484 484 256 256 256 Temp. Com Com Com Com Com Com LUTs (K) 20 20 20 20 20 20 Part Number LFE2M35SE-5F672C LFE2M35SE-6F672C LFE2M35SE-7F672C LFE2M35SE-5F484C LFE2M35SE-6F484C LFE2M35SE-7F484C LFE2M35SE-5F256C LFE2M35SE-6F256C LFE2M35SE-7F256C I/Os 410 410 410 303 303 303 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 672 672 672 484 484 484 256 256 256 Temp. Com Com Com Com Com Com Com Com Com LUTs (K) 35 35 35 35 35 35 35 35 35 Part Number LFE2M50SE-5F900C LFE2M50SE-6F900C LFE2M50SE-7F900C LFE2M50SE-5F672C LFE2M50SE-6F672C LFE2M50SE-7F672C LFE2M50SE-5F484C LFE2M50SE-6F484C LFE2M50SE-7F484C I/Os 410 410 410 372 372 372 270 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 900 900 900 672 672 672 484 484 484 Temp. Com Com Com Com Com Com Com Com Com LUTs (K) 50 50 50 50 50 50 50 50 50 5-20 Lattice Semiconductor Part Number LFE2M70SE-5F1152C LFE2M70SE-6F1152C LFE2M70SE-7F1152C LFE2M70SE-5F900C LFE2M70SE-6F900C LFE2M70SE-7F900C Part Number LFE2M100SE-5F1152C LFE2M100SE-6F1152C LFE2M100SE-7F1152C LFE2M100SE-5F900C LFE2M100SE-6F900C LFE2M100SE-7F900C I/Os 436 436 436 416 416 416 I/Os 520 520 520 416 416 416 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 1152 1152 1152 900 900 900 Pins 1152 1152 1152 900 900 900 Temp. Com Com Com Com Com Com Temp. Com Com Com Com Com Com LUTs (K) 70 70 70 70 70 70 LUTs (K) 100 100 100 100 100 100 5-21 Lattice Semiconductor Industrial Part Number LFE2M20SE-5F484I LFE2M20SE-6F484I LFE2M20SE-5F256I LFE2M20SE-6F256I I/Os 304 304 140 140 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Ordering Information LatticeECP2/M Family Data Sheet Package fpBGA fpBGA fpBGA fpBGA Pins 484 484 256 256 Temp. Ind Ind Ind Ind LUTs (K) 20 20 20 20 Part Number LFE2M35SE-5F672I LFE2M35SE-6F672I LFE2M35SE-5F484I LFE2M35SE-6F484I LFE2M35SE-5F256I LFE2M35SE-6F256I I/Os 410 410 303 303 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 672 672 484 484 256 256 Temp. Ind Ind Ind Ind Ind Ind LUTs (K) 35 35 35 35 35 35 Part Number LFE2M50SE-5F900I LFE2M50SE-6F900I LFE2M50SE-5F672I LFE2M50SE-6F672I LFE2M50SE-5F484I LFE2M50SE-6F484I I/Os 410 410 372 372 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Pins 900 900 672 672 484 484 Temp. Ind Ind Ind Ind Ind Ind LUTs (K) 50 50 50 50 50 50 Part Number LFE2M70SE-5F1152I LFE2M70SE-6F1152I LFE2M70SE-5F900I LFE2M70SE-6F900I I/Os 436 436 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 1152 1152 900 900 Temp. Ind Ind Ind Ind LUTs (K) 70 70 70 70 Part Number LFE2M100SE-5F1152I LFE2M100SE-6F1152I LFE2M100SE-5F900I LFE2M100SE-6F900I I/Os 520 520 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package fpBGA fpBGA fpBGA fpBGA Pins 1152 1152 900 900 Temp. Ind Ind Ind Ind LUTs (K) 100 100 100 100 5-22 Lattice Semiconductor LatticeECP2M S-Series Devices, Lead-Free Packaging Commercial Part Number LFE2M20SE-5FN484C LFE2M20SE-6FN484C LFE2M20SE-7FN484C LFE2M20SE-5FN256C LFE2M20SE-6FN256C LFE2M20SE-7FN256C I/Os 304 304 304 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 484 256 256 256 Temp. Com Com Com Com Com Com LUTs (K) 20 20 20 20 20 20 Part Number LFE2M35SE-5FN672C LFE2M35SE-6FN672C LFE2M35SE-7FN672C LFE2M35SE-5FN484C LFE2M35SE-6FN484C LFE2M35SE-7FN484C LFE2M35SE-5FN256C LFE2M35SE-6FN256C LFE2M35SE-7FN256C I/Os 410 410 410 303 303 303 140 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 672 484 484 484 256 256 256 Temp. Com Com Com Com Com Com Com Com Com LUTs (K) 35 35 35 35 35 35 35 35 35 Part Number LFE2M50SE-5FN900C LFE2M50SE-6FN900C LFE2M50SE-7FN900C LFE2M50SE-5FN672C LFE2M50SE-6FN672C LFE2M50SE-7FN672C LFE2M50SE-5FN484C LFE2M50SE-6FN484C LFE2M50SE-7FN484C I/Os 410 410 410 372 372 372 270 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 900 900 900 672 672 672 484 484 484 Temp. Com Com Com Com Com Com Com Com Com LUTs (K) 50 50 50 50 50 50 50 50 50 Part Number LFE2M70SE-5FN1152C LFE2M70SE-6FN1152C LFE2M70SE-7FN1152C LFE2M70SE-5FN900C LFE2M70SE-6FN900C LFE2M70SE-7FN900C I/Os 436 436 436 416 416 416 Voltage 1.2V 1.2V 1.2V 1.2V 416 416 Grade -5 -6 -7 -5 -6 -7 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 1152 900 900 900 Temp. Com Com Com Com Com Com LUTs (K) 70 70 70 70 70 70 5-23 Lattice Semiconductor Part Number LFE2M100SE-5FN1152C LFE2M100SE-6FN1152C LFE2M100SE-7FN1152C LFE2M100SE-5FN900C LFE2M100SE-6FN900C LFE2M100SE-7FN900C I/Os 520 520 520 416 416 416 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -7 -5 -6 -7 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 1152 900 900 900 Temp. Com Com Com Com Com Com LUTs (K) 100 100 100 100 100 100 5-24 Lattice Semiconductor Industrial Part Number LFE2M20SE-5FN484I LFE2M20SE-6FN484I LFE2M20SE-5FN256I LFE2M20SE-6FN256I I/Os 304 304 140 140 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Ordering Information LatticeECP2/M Family Data Sheet Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 484 484 256 256 Temp. Ind Ind Ind Ind LUTs (K) 20 20 20 20 Part Number LFE2M35SE-5FN672I LFE2M35SE-6FN672I LFE2M35SE-5FN484I LFE2M35SE-6FN484I LFE2M35SE-5FN256I LFE2M35SE-6FN256I I/Os 410 410 303 303 140 140 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 672 672 484 484 256 256 Temp. Ind Ind Ind Ind Ind Ind LUTs (K) 35 35 35 35 35 35 Part Number LFE2M50SE-5FN900I LFE2M50SE-6FN900I LFE2M50SE-5FN672I LFE2M50SE-6FN672I LFE2M50SE-5FN484I LFE2M50SE-6FN484I I/Os 410 410 372 372 270 270 Voltage 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 900 900 672 672 484 484 Temp. Ind Ind Ind Ind Ind Ind LUTs (K) 50 50 50 50 50 50 Part Number LFE2M70SE-5FN1152I LFE2M70SE-6FN1152I LFE2M70SE-5FN900I LFE2M70SE-6FN900I I/Os 436 436 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 900 900 Temp. Ind Ind Ind Ind LUTs (K) 70 70 70 70 Part Number LFE2M100SE-5FN1152I LFE2M100SE-6FN1152I LFE2M100SE-5FN900I LFE2M100SE-6FN900I I/Os 520 520 416 416 Voltage 1.2V 1.2V 1.2V 1.2V Grade -5 -6 -5 -6 Package Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Lead-Free fpBGA Pins 1152 1152 900 900 Temp. Ind Ind Ind Ind LUTs (K) 100 100 100 100 5-25 LatticeECP2/M Family Data Sheet Supplemental Information September 2006 Data Sheet DS1006 For Further Information A variety of technical notes for the LatticeECP2 family are available on the Lattice web site at www.latticesemi.com. * * * * * * * LatticeECP2M SERDES/PCS Usage Guide (TN1124) LatticeECP2/M sysIO Usage Guide (TN1102) LatticeECP2/M sysCLOCK PLL Design and Usage Guide (TN1103) LatticeECP2/M Memory Usage Guide (TN1104) LatticeECP2/M High-Speed I/O Interface (TN1105) Power Estimation and Management for LatticeECP2/M Devices (TN1106) LatticeECP2/M sysDSP Usage Guide (TN1107) * LatticeECP2/M sysCONFIG Usage Guide (TN1108) * LatticeECP2/M Configuration Encryption Usage Guide (TN1109) * LatticeECP2/M Soft Error Detection (SED) Usage Guide (TN1113) For further information about interface standards refer to the following web sites: * JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org * PCI: www.pcisig.com (c) 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS1006 Further Info_01.0 LatticeECP2/M Family Data Sheet Revision History August 2008 Date February 2006 August 2006 Version 01.0 01.1 Section -- Introduction Updated Table 1-1 "LatticeECP2 Family Selection Guide" Architecture Updated figure 2-2 "PFU Diagram" Updated figure 2-13 "Secondary Clock Regions ECP2-50" Updated figure 2-25 "PIC Diagram" Updated figure 2-26 "Input Register Block for Left, Right and Bottom Edges" Updated figure 2-28 "Output Register Block for Left, Right and Bottom Edges" Updated figure 2-30 "DQS Input Routing for Left and Right Edges" Updated figure 2-32 "Edge Clock, DLL Calibration and DQS Local Bus Distribution" Table 2-15 Selectable Master clock (CCLK) frequencies Removed frequencies 15,20,21,22,23,30,34,41,45,51,55,60 Replaced "CLKINDEL" with "CLKO" Updated SED section Qualified device migration capability when using DQS banks for DDR interfaces DC and Switching Characteristics Added VCCPLL to the Recommended Operating Conditions Table Remove Note 5 from "Hot Specifications" section Added note 7 & 8 to "Initialization Supply current Table Change Note 6 - "...down to 95MHz" to "...down to 95MHz for DDR and 133MHz for DDR2" New "Typical Building Block Function Performance" numbers New External Switching Characteristics numbers New Internal Switching Characteristics numbers New Family Timing Adders numbers Updated Timings for GPLLs, SPLLs and DLLs Added sysConfig waveforms. Remove HSTL15D_II from sysIO Recommended Operating Condition Table Updated Supply and initialization currents for ECP2-50 Pinout Information Added VCCPLL to the Signal Descriptions Table Updated Logic signal Connections tables to include 484-fpBGA for the ECP2-50. Added Logic signal Connections tables for ECP2-12 devices. Updated Pin Information Summary table to include ECP2-12. Updated Power Supply and NC Connections table to include ECP2-12. Added Note 2 to DDR Strobe (DQS) Pin Table Added Information on: PCI, DDR & SPI4.2 Capabilities of the devicePackage combination (c) 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Data Sheet DS1006 Change Summary Initial release. www.latticesemi.com 7-1 DS1006 Revision History Lattice Semiconductor Date August 2006 (cont.) Version 01.1 (cont.) Section Pinout Information (cont.) Ordering Information September 2006 September 2006 02.0 02.1 Multiple DC and Switching Characteristics Revision History LatticeECP2/M Family Data Sheet Change Summary Added Information on: Available Device Resources per Packaged Device table Updated ordering part number table to include ECP2-12. Updated topside mark drawing Added information regarding LatticeECP2M support throughout. Added Receiver Total Jitter Tolerance Specification table. Removed power-up requirements for proper configuration footnote in Recommended Operating Conditions table. December 2006 02.2 Introduction Architecture LatticeECP2M Selection Guide table has been updated. Figure 2-16. Per Region Secondary Clock Selection has been updated. Figure 2-39. Simplified Channel Block Diagram for SERDES and PCS has been updated. DC and Switching Footnotes have been added to Recommended Operating Conditions DC Electrical Characteristics table has been updated. Supply Current (Standby) tables have been updated. Initialization Supply Current table have been updated. Updated timing numbers to include LFE2-12E (rev A 0.08) Pinout Information Ordering Information February 2007 March 2007 02.3 02.4 Architecture DC and Switching Characteristics Introduction Architecture DC and Switching Ordering Information April 2007 02.6 Introduction Ordering Information July 2007 02.7 Architecture DC and Switching Updated to include the entire ECP2 device information as well as 256fpBGA and 484-fpBGA pin information for the ECP2M35E. Updated to include the entire ECP2 and ECP2M device ordering information. Updated EBR Asynchronous Reset section. Power-sequencing footnotes have been added to the Recommended Operating Conditions. DDR2 performance has been updated to 266MHz. Added "Security Series" to the LatticeECP2 and LatticeECP2M families. Enhanced Configuration Option section updated. Recommended Operating Conditions table - footnote 4 updated. "Security Series" ordering part numbers added. LatticeECP2M family table has been updated for user I/O counts. LatticeECP2M family ordering part number section has been updated to add 1152-fpBGA package for the ECP2M70 and ECP2M100. Updated text in Ripple Mode section. ECP2/M Supply Current information has been updated. Typical Building Block Function Performance, External Switching Characteristics, Internal Switching Characteristics, Family Timing Adders, sysCLOCK GPLL Timing, sysCLOCK SPLL Timing, DLL Timing and sysCONFIG Port Timing Specifications have been updated (timing rev. A 0.10). SERDES timing information has been updated. PCI Express timing information has been updated. Added LatticeECP2M20 pinout information. 1156-fpBGA package option has been removed from the LatticeECP2M family. Table 2-16. Selectable Master Clock (CCLK) Frequencies During Configuration table has been updated. Supply Current (Standby) table has been updated. DSP Function timing has been updated. March 2007 02.5 Pinout Information August 2007 02.8 Introduction Architecture DC and Switching 7-2 Lattice Semiconductor Date August 2007 (cont.) Version 02.8 (cont.) Section DC and Switching (cont.) Pinout Information Ordering Information September 2007 February 2008 02.9 03.0 Pinout Information Architecture DC and Switching Revision History LatticeECP2/M Family Data Sheet Change Summary sysCLOCK GPLL timing has been updated. Added ECP2M50 (484/672/900-fpBGA), ECP2M70 (900-fpBGA) and ECP2M100 (900-fpBGA) pinout information. 1156-fpBGA package option has been removed from the LatticeECP2M family. Added Thermal Management text section. Added LVCMOS33D description. LatticeECP2M Supply Current has been updated. Typical Building Block Function Performance, External Switching Characteristics, Internal Switching Characteristics, Family Timing Adders, sysCLOCK GPLL Timing, sysCLOCK SPLL Timing, DLL Timing and sysCONFIG Port Timing Specifications have been updated (timing rev. A 0.11). Figure 3-9. Read/Write Mode (Normal) and Figure 3-10. Read/Write Mode with Input and Output Registers have been updated. Table 3-8. Channel output Jitter (Max) has been updated. Pinout Information April 2008 June 2008 03.1 03.2 Pinout Information Introduction Architecture DC and Switching Characteristics August 2008 03.3 Architecture Pinout Information Signal description has been updated. Added 1152-fpBGA pinouts for the ECP2M70 and ECP2M100. Available DDR Interfaces per I/O Bank for the LFE2M35 (484/672fpBGA) have been updated. Family Selection Guide table - Updated number of EBR SRAM Blocks for the ECP2-70 device. Removed Read-Before-Write sysMEM EBR mode. Clarification of the operation of the secondary clock regions. Removed Read-Before-Write sysMEM EBR mode. Clarification of the operation of the secondary clock regions. Added information for [LOC]DQ[num] to Signal Descriptions table. 7-3 |
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